Managing standby and active mode leakage power in deep sub-micron design. - Lawrence T. Clark; Rakesh Patel; Timothy S. Beatty (ISLPED, 2004)

A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. - Jonathan R. Haigh; Michael W. Wilkerson; Jay B. Miller; Timothy S. Beatty; Stephen J. Strazdus; Lawrence T. Clark (IEEE J. Solid State Circuits, 2005)