A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. - Subhankar Pal; Dong-Hyeon Park; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (VLSI Circuits, 2019)

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. - Dong-Hyeon Park; Subhankar Pal; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (IEEE J. Solid State Circuits, 2020)