A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking. - Alvin Leng Sun Loke; Robert K. Barnes; Tin Tin Wee; Michael M. Oshima; Charles E. Moore; Ronald R. Kennedy; Jim O. Barnes; Robert A. Zimmer; Kari L. Arave; H. Herman M. Pang; Tom E. Cynkar; Aaron M. Volz; et al. (CICC, 2005)

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. - Alvin Leng Sun Loke; Robert K. Barnes; Tin Tin Wee; Michael M. Oshima; Charles E. Moore; Ronald R. Kennedy; Michael J. Gilsdorf (IEEE J. Solid State Circuits, 2006)

Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links. - Alvin Leng Sun Loke; Bruce Andrew Doyle; Michael M. Oshima; Wade L. Williams; Robert G. Lewis; Charles Lin Wang; Audie Hanpachern; Karen M. Tucker; Prashanth Gurunath; Gladney C. Asada; Chad O. Lackey; Tin Tin Wee; et al. (CICC, 2009)

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. - Bruce Andrew Doyle; Alvin Leng Sun Loke; Sanjeev K. Maheshwari; Charles Lin Wang; Dennis Michael Fischette; Jeffrey G. Cooper; Sanjeev K. Aggarwal; Tin Tin Wee; Chad O. Lackey; Harishkumar S. Kedarnath; Michael M. Oshima; Gerry R. Talbot; et al. (A-SSCC, 2011)

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. - Alvin Leng Sun Loke; Bruce Andrew Doyle; Sanjeev K. Maheshwari; Dennis Michael Fischette; Charles Lin Wang; Tin Tin Wee; Emerson S. Fang (IEEE J. Solid State Circuits, 2012)

Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. - Alvin Leng Sun Loke; Da Yang 007; Tin Tin Wee; Jonathan L. Holland; Patrick Isakanian; Kern Rim; Sam Yang; Jacob S. Schneider; Giri Nallapati; Sreeker Dundigal; Hasnain Lakdawala; Behnam Amelifard; et al. (CICC, 2019)