An Optimal Algorithm for Floorplan Area Optimization. - Ting-Chi Wang; D. F. Wong 001 (DAC, 1990)

Efficient shape curve construction in floorplan design. - Ting-Chi Wang; D. F. Wong 001 (EURO-DAC, 1991)

A Graph Theoretic Technique to Speed up Floorplan Area Optimization. - Ting-Chi Wang; D. F. Wong 001 (DAC, 1992)

Optimal floorplan area optimization. - Ting-Chi Wang; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A note on the Complexity of Stockmeyer's floorplan Optimization Technique. - Ting-Chi Wang; D. F. Wong 001 (Algorithmic Aspects of VLSI Layout, 1993)

On over-the-cell channel routing. - Ting-Chi Wang; D. F. Wong 001; Yachyang Sun; C. K. Wong (EURO-DAC, 1993)

A Graph Partitioning Problem for Multiple-chip Design. - Yao-Ping Chen; Ting-Chi Wang; D. F. Wong 001 (ISCAS, 1993)

Graph-based techniques to speed up floorplan area optimization. - Ting-Chi Wang; D. F. Wong 001 (Integr., 1993)

Performance-driven channel pin assignment algorithms. - T. W. Her; Ting-Chi Wang; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Optimal net assignment. - Ting-Chi Wang; Martin D. F. Wong; Yachyang Sun; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Routing for symmetric FPGAs and FPICs. - Yachyang Sun; Ting-Chi Wang; Chak-Kuen Wong; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Faster and Better Spectral Algorithms for Multi-Way Partitioning. - Jan-Yang Chang; Yu-Chen Liu; Ting-Chi Wang (ASP-DAC, 1999)

Feasible two-way circuit partitioning with complex resource constraints. - Hsun-Cheng Lee; Ting-Chi Wang (ASP-DAC, 2000)

On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. - Jennifer Dworak; Michael R. Grimaila; Brad Cobb; Ting-Chi Wang; Li-C. Wang; M. Ray Mercer (Asian Test Symposium, 2000)

On accelerating slicing floorplan design with boundary constraints. - En-Cheng Liu; Tu-Hsing Lin; Ting-Chi Wang (ISCAS, 2000)

Module placement with boundary constraints using the sequence-pair representation. - Jianbang Lai; Ming-Shiun Lin; Ting-Chi Wang; Li-C. Wang (ASP-DAC, 2001)

Power minization in LUT-based FPGA technology mapping. - Zhi-Hong Wang; En-Cheng Liu; Jianbang Lai; Ting-Chi Wang (ASP-DAC, 2001)

Module placement with pre-placed modules using the B*-tree representation. - Yi-He Jiang; Jianbang Lai; Ting-Chi Wang (ISCAS (5), 2001)

Slicing floorplan design with boundary-constrained modules. - En-Cheng Liu; Ming-Shiun Lin; Jianbang Lai; Ting-Chi Wang (ISPD, 2001)

Module placement with pre-placed modules using the corner block list representation. - S. Dhamdhere; Ningyu Zhou; Ting-Chi Wang (ISCAS (1), 2002)

Optimal circuit clustering with variable interconnect delay. - Cliff C. N. Sze; Ting-Chi Wang (ISCAS (4), 2002)

Multi-Level Circuit Clustering for Delay Minimization. - Cliff C. N. Sze; Ting-Chi Wang (IWLS, 2002)

Performance-driven multi-level clustering for combinational circuits. - Chin Ngai Sze; Ting-Chi Wang (ASP-DAC, 2003)

Optimal circuit clustering for delay minimization under a more general delay model. - Cliff C. N. Sze; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Multilevel circuit clustering for delay minimization. - Cliff C. N. Sze; Ting-Chi Wang; Li-C. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. - Zhong-Ching Lu; Ting-Chi Wang (ASP-DAC, 2005)

Maze routing with OPC consideration. - Yun-Ru Wu; Ming-Chao Tsai; Ting-Chi Wang (ASP-DAC, 2005)

Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. - Hao-Yueh Hsieh; Ting-Chi Wang (ISCAS (2), 2005)

Post-routing redundant via insertion for yield/reliability improvement. - Kuang-Yao Lee; Ting-Chi Wang (ASP-DAC, 2006)

Post-routing redundant via insertion and line end extension with via density consideration. - Kuang-Yao Lee; Ting-Chi Wang; Kai-Yuan Chao (ICCAD, 2006)

Fast Buffered Delay Estimation Considering Process Variations. - Tien-Ting Fang; Ting-Chi Wang (ASP-DAC, 2007)

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. - Chung-Wei Lin; Ming-Chao Tsai; Kuang-Yao Lee; Tai-Chen Chen; Ting-Chi Wang; Yao-Wen Chang (ASP-DAC, 2007)

A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. - Pei-Ci Wu; Jhih-Rong Gao; Ting-Chi Wang (ASP-DAC, 2007)

A new global router for modern designs. - Jhih-Rong Gao; Pei-Ci Wu; Ting-Chi Wang (ASP-DAC, 2008)

An MILP-based wire spreading algorithm for PSM-aware layout modification. - Ming-Chao Tsai; Yung-Chia Lin; Ting-Chi Wang (ASP-DAC, 2008)

A generalized network flow based algorithm for power-aware FPGA memory mapping. - Tien-Yuan Hsu; Ting-Chi Wang (DAC, 2008)

NTHU-Route 2.0: a fast and stable global router. - Yen-Jung Chang; Yu-Ting Lee; Ting-Chi Wang (ICCAD, 2008)

Optimal post-routing redundant via insertion. - Kuang-Yao Lee; Cheng-Kok Koh; Ting-Chi Wang; Kai-Yuan Chao (ISPD, 2008)

Fast and Optimal Redundant Via Insertion. - Kuang-Yao Lee; Cheng-Kok Koh; Ting-Chi Wang; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Congestion-Constrained Layer Assignment for Via Minimization in Global Routing. - Tsung-Hsien Lee; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Slicing Floorplans. - Ting-Chi Wang; Martin D. F. Wong (Handbook of Algorithms for Physical Design Automation, 2008)

Redundant via insertion with wire bending. - Kuang-Yao Lee; Shing-Tung Lin; Ting-Chi Wang (ISPD, 2009)

Robust layer assignment for via optimization in multi-layer global routing. - Tsung-Hsien Lee; Ting-Chi Wang (ISPD, 2009)

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. - De-Yu Liu; Wai-Kei Mak; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2010)

GLADE: A modern global router considering layer directives. - Yen-Jung Chang; Tsung-Hsien Lee; Ting-Chi Wang (ICCAD, 2010)

Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing. - Tsung-Hsien Lee; Ting-Chi Wang (ICCAD, 2010)

NTHU-Route 2.0: A Robust Global Router for Modern Designs. - Yen-Jung Chang; Yu-Ting Lee; Jhih-Rong Gao; Pei-Ci Wu; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Enhanced Double Via Insertion Using Wire Bending. - Kuang-Yao Lee; Shing-Tung Lin; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Optimal Double Via Insertion With On-Track Preference. - Kuang-Yao Lee; Ting-Chi Wang; Cheng-Kok Koh; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Simultaneous redundant via insertion and line end extension for yield optimization. - Shing-Tung Lin; Kuang-Yao Lee; Ting-Chi Wang; Cheng-Kok Koh; Kai-Yuan Chao (ASP-DAC, 2011)

An enhanced global router with consideration of general layer directives. - Tsung-Hsien Lee; Yen-Jung Chang; Ting-Chi Wang (ISPD, 2011)

Through-Silicon Via Planning in 3-D Floorplanning. - Ming-Chao Tsai; Ting-Chi Wang; Ting Ting Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Pad Assignment for Die-Stacking System-in-Package Design. - Wai-Kei Mak; Yu-Chen Lin; Chris Chu; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. - Bo-Han Zeng; Ren-Song Tsay; Ting-Chi Wang (ASP-DAC, 2013)

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. - Cha-Ru Li; Wai-Kei Mak; Ting-Chi Wang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Redundant-via-aware ECO routing. - Hsi-An Chien; Ting-Chi Wang (ASP-DAC, 2014)

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. - Wen-Hao Liu 001; Min-Sheng Chang; Ting-Chi Wang (DAC, 2014)

Density-aware Detailed Placement with Instant Legalization. - Sergiy Popovych; Hung-Hao Lai; Chieh-Min Wang; Yih-Lang Li; Wen-Hao Liu 001; Ting-Chi Wang (DAC, 2014)

Mask-cost-aware ECO routing∗. - Hsi-An Chien; Zhen-Yu Peng; Yun-Ru Wu; Ting-Hsiung Wang; Hsin-Chang Lin; Chi-Feng Wu; Ting-Chi Wang (DATE, 2014)

Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. - Wen-Hao Liu 001; Tzu-Kai Chien; Ting-Chi Wang (DATE, 2014)

A study on the use of parallel wiring techniques for sub-20nm designs. - Rickard Ewetz; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang; Cheng-Kok Koh (ACM Great Lakes Symposium on VLSI, 2014)

A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. - Wen-Hao Liu 001; Zhen-Yu Peng; Ting-Chi Wang (ICCAD, 2014)

A study on unroutable placement recognition. - Wen-Hao Liu 001; Tzu-Kai Chien; Ting-Chi Wang (ISPD, 2014)

Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction. - Chih-Hung Liu 001; Chun-Xun Lin; I-Che Chen; D. T. Lee; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography. - Hsi-An Chien; Szu-Yuan Han; Ye-Hong Chen; Ting-Chi Wang (ISPD, 2015)

On Refining Row-Based Detailed Placement for Triple Patterning Lithography. - Hsi-An Chien; Ye-Hong Chen; Szu-Yuan Han; Hsiu-Yu Lai; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. - Wen-Hao Liu 001; Tzu-Kai Chien; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Negotiation-based track assignment considering local nets. - Man-Pan Wong; Wen-Hao Liu 001; Ting-Chi Wang (ASP-DAC, 2016)

Online slack-time binning for IO-registered die-to-die interconnects. - Chih-Chieh Zheng; Shi-Yu Huang; Shyue-Kung Lu; Ting-Chi Wang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2016)

Delay-driven layer assignment for advanced technology nodes. - Szu-Yuan Han; Wen-Hao Liu 001; Rickard Ewetz; Cheng-Kok Koh; Kai-Yuan Chao; Ting-Chi Wang (ASP-DAC, 2017)

On refining standard cell placement for self-aligned double patterning. - Ye-Hong Chen; Sheng-He Wang; Ting-Chi Wang (DATE, 2017)

A routing framework for technology migration with bump encroachment. - Po-Yi Wu; Wai-Kei Mak; Ting-Chi Wang; Cheng Zhuo; Kassan Unda; Yiyu Shi 001 (Integr., 2017)

A practical detailed placement algorithm under multi-cell spacing constraints. - Yu-Hsiang Cheng; Ding-Wei Huang; Wai-Kei Mak; Ting-Chi Wang (ICCAD, 2018)

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. - Atsushi Takahashi 001; Shimpei Sato; Hiroki Ogura; Yu-Min Sung; Ting-Chi Wang (ISVLSI, 2018)

A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks*. - Yi-Cheng Zhao; Yu-Chieh Lin; Ting-Chi Wang; Ting-Hsiung Wang; Yun-Ru Wu; Hsin-Chang Lin; Shu-Yi Kao (DATE, 2019)

RDTA: An Efficient Routability-Driven Track Assignment Algorithm. - Genggeng Liu; Zhen Zhuang; Wenzhong Guo; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2019)

Audio Adversarial Examples Generation with Recurrent Neural Networks*. - Kuei-Huan Chang; Po-Hao Huang; Honggang Yu; Yier Jin; Ting-Chi Wang (ASP-DAC, 2020)

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. - Xinghai Zhang; Zhen Zhuang; Genggeng Liu; Xing Huang 001; Wen-Hao Liu 001; Wenzhong Guo; Ting-Chi Wang (DATE, 2020)

Forensic Artifacts of Network Traffic on WeChat Calls. - Da-Yu Kao; Ting-Chi Wang; Fu-Ching Tsai (ICACT, 2020)

An Algorithm for Rule-based Layout Pattern Matching. - Sheng-Hao Wang; Yen-Jong Chen; Ting-Chi Wang; Oscar Chen (ICCAD, 2020)

MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router. - Weida Zhu; Xinghai Zhang; Genggeng Liu; Wenzhong Guo; Ting-Chi Wang (VLSI-DAT, 2020)

Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. - Bo-Yang Chen; Chi-Chun Fang; Wai-Kei Mak; Ting-Chi Wang (ISPD, 2021)

HybridGP: Global Placement for Hybrid-Row-Height Designs. - Kuan-Yu Chen; Hsiu-Chu Hsu; Wai-Kei Mak; Ting-Chi Wang (ASP-DAC, 2022)

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. - Meng-Yun Liu; Yu-Cheng Lai; Wai-Kei Mak; Ting-Chi Wang (ICCAD, 2022)

On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network. - Kuei-Huan Chang; Hsin-Hung Pan; Ting-Chi Wang; Po-Yuan Chen; Cindy Chin-Fang Shen (ISQED, 2022)

LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. - Lieqiu Jiang; Zepeng Li; Chenpeng Bao; Genggeng Liu; Xing Huang 001; Wen-Hao Liu 001; Ting-Chi Wang (VLSI-SoC, 2022)

SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. - Yidan Jing; Liliang Yang; Zhen Zhuang; Genggeng Liu; Xing Huang 001; Wen-Hao Liu 001; Ting-Chi Wang (VLSI-SoC, 2022)

Generation of Black-box Audio Adversarial Examples Based on Gradient Approximation and Autoencoders. - Po-Hao Huang; Honggang Yu; Max Panoff; Ting-Chi Wang (ACM J. Emerg. Technol. Comput. Syst., 2022)

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. - Genggeng Liu; Xinghai Zhang; Wenzhong Guo; Xing Huang 001; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints. - Chun-Wei Chiu; Yun-Kai Fang; Shao-Ting Chung; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2023)

Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. - Syuan-Han Liang; Tsu-Ling Hsiung; Wai-Kei Mak; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2023)

Fast and Accurate Detection of Audio Adversarial Examples. - Po-Hao Huang; Yung-Yuan Lan; Wilbert Harriman; Venesia Chiuwanara; Ting-Chi Wang (ISCAS, 2023)

Routability-aware Placement Guidance Generation for Mixed-size Designs. - Chieh-Yu Cheng; Ting-Chi Wang (ISQED, 2023)

A Robust Routing Guide Generation Approach for Mixed-Size Designs. - Zhi-Hong Lee; Chen-Han Lu; Hsin-Hung Pan; Ting-Chi Wang; Po-Yuan Chen; Cindy Chin-Fang Shen (MLCAD, 2023)

A Fast and Robust Global Router with Capacity Reduction Techniques. - Yun-Kai Fang; Ye-Chih Lin; Ting-Chi Wang (ASPDAC, 2024)

An Effective Netlist Planning Approach for Double-sided Signal Routing. - Tzu-Chuan Lin; Fang-Yu Hsu; Wai-Kei Mak; Ting-Chi Wang (ASPDAC, 2024)

A Hybrid Approach to Reverse Engineering on Combinational Circuits. - Wuqian Tang; Yi-Ting Li; Kai-Po Hsu; Kuan-Ling Chou; You-Cheng Lin; Chia-Feng Chien; Tzu-Li Hsu; Yung-Chih Chen; Ting-Chi Wang; Shih-Chieh Chang; TingTing Hwang; Chun-Yao Wang (DATE, 2024)

A Bounding Box-based Net Partitioning Method for Double-sided Routing. - Fang-Yu Hsu; Tzu-Chuan Lin; Wai-Kei Mak; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2024)

A Hypergraph Partitioner Utilizing a Novel Graph Generative Model. - Magi Chen; Ting-Chi Wang (ICCAD, 2024)

An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing. - Che-Ping Tsai; Fang-Yu Hsu; Wai-Kei Mak; Ting-Chi Wang (ICCAD, 2024)

SMT-Based Layout Synthesis Approaches for Quantum Circuits. - Zi-Hao Guo; Ting-Chi Wang (ISPD, 2024)

Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan Design. - Ting-Chi Wang (ISPD, 2024)

A Machine Learning-Assisted Placement Flow with Pin Accessibility Awareness. - Min-Feng Hsieh; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2025)

An Effective and Efficient Qubit Mapping Approach for Trapped-Ion Quantum Computers. - Liang-Yu Lai; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2025)

Analyzing and Enhancing the Reliability of Vision Transformer Models Against Soft Errors. - En-Yu Liao; Ting-Chi Wang (ISCAS, 2025)

A PPA- and Security-Aware Physical Design Flow. - Chun-Wei Chiu; Ting-Chi Wang (ISQED, 2025)

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. - Johann Knechtel; Mohammad Eslami; Peng Zou; Min Wei; Xingyu Tong 001; Binggang Qiu; Zhijie Cai; Guohao Chen 001; Benchao Zhu; Jiawei Li; Jun Yu 010; Jianli Chen; et al. (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay. - Huayang Cai; Pengcheng Huang; Genggeng Liu; Xing Huang 001; Yidan Jing; Wenhao Liu 001; Ting-Chi Wang (ACM Trans. Design Autom. Electr. Syst., 2025)

A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree. - Zhenkun Lin; Genggeng Liu; Xing Huang 001; Yibo Lin; Jixin Zhang; Wen-Hao Liu 001; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)