Nanometer-scale standard cell library for enhanced redundant via1 insertion rate. - Tsang-Chi Kan; Shih-Hsien Yang; Ting-Feng Chang; Shanq-Jang Ruan (ACM Great Lakes Symposium on VLSI, 2011)

Enhanced Redundant via Insertion with Multi-via Mechanisms. - Ting-Feng Chang; Tsang-Chi Kan; Shih-Hsien Yang; Shanq-Jang Ruan (ISVLSI, 2011)

Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate. - Tsang-Chi Kan; Shih-Hsien Yang; Ting-Feng Chang; Shanq-Jang Ruan (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration. - Tsang-Chi Kan; Shanq-Jang Ruan; Ting-Feng Chang; Shih-Hsien Yang (Circuits Syst. Signal Process., 2015)