A 0.43pJ/bit true random number generator. - Ting-Kuei Kuan; Yu-Hsuan Chiang; Shen-Iuan Liu (A-SSCC, 2014)

A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction. - Ting-Kuei Kuan; Shen-Iuan Liu (VLSIC, 2015)

A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops. - Ting-Kuei Kuan; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth. - Chih-Lu Wei; Ting-Kuei Kuan; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider. - Kai-Hui Zeng; Ting-Kuei Kuan; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A digital MDLL using switched biasing technique to reduce low-frequency phase noise. - Chi-Huan Chiang; Chang-Cheng Huang; Ting-Kuei Kuan; Shen-Iuan Liu (A-SSCC, 2016)

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques. - Ting-Kuei Kuan; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2016)

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. - Ting-Kuei Kuan; Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2018)

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2019)

A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang (IEEE J. Solid State Circuits, 2020)