DLL-based programmable clock multiplier using differential toggle-pulsed latch. - Chorng-Sii Hwang; Ting-Li Chu; Po-Hsun Chen (SoCC, 2013)

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability. - Ting-Li Chu; Sin-Hong Yu; Chorng-Sii Hwang (VLSI Design, 2013)

A clock generator based on multiplying delay-locked loop. - Chorng-Sii Hwang; Ting-Li Chu; Wen-Cheng Chen (SoCC, 2014)

All-digital deskew buffer using a hybrid control scheme. - Ting-Li Chu; Wen-Yu Chu; Yasuyoshi Fujii; Chorng-Sii Hwang (SoCC, 2015)

Corrigendum to "High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability". - Ting-Li Chu; Sin-Hong Yu; Chorng-Sii Hwang (VLSI Design, 2017)