Faster defect localization in nanometer technology based on defective cell diagnosis. - Manish Sharma; Wu-Tung Cheng; Ting-Pu Tai; Y. S. Cheng; Will Hsu; Chen Liu; Sudhakar M. Reddy; Albert Mann (ITC, 2007)

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. - Manish Sharma; Brady Benware; Lei Ling; David Abercrombie; Lincoln Lee; Martin Keim; Huaxing Tang; Wu-Tung Cheng; Ting-Pu Tai; Yi-Jung Chang; Reinhart Lin; Albert Mann (ITC, 2008)

Customized Algorithms for High Performance Memory Test in Advanced Technology Node. - Shomo Chen; Ning Huang; Ting-Pu Tai; Actel Niu (Asian Test Symposium, 2009)

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Ting-Pu Tai; Feng-Ming Kuo; Yuan-Shih Chen (Asian Test Symposium, 2009)

Case study of scan chain diagnosis and PFA on a low yield wafer. - Yu Huang 005; Brady Benware; Wu-Tung Cheng; Ting-Pu Tai; Feng-Ming Kuo; Yuan-Shih Chen (ITC, 2010)

Test cycle power optimization for scan-based designs. - Kun-Han Tsai; Yu Huang 005; Wu-Tung Cheng; Ting-Pu Tai; Augusli Kifli (ITC, 2010)

Diagnosing timing related cell internal defects for FinFET technology. - Huaxing Tang; Ting-Pu Tai; Wu-Tung Cheng; Brady Benware; Friedrich Hapke (VLSI-DAT, 2015)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Automotive semiconductor test. - Steve Pateras; Ting-Pu Tai (VLSI-DAT, 2017)

Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs. - Khader S. Abdel-Hafez; Michael Dsouza; Likith Kumar Manchukonda; Elddie Tsai; Karthikeyan Natarajan; Ting-Pu Tai; Wenhao Hsueh; Smith Lai (ITC, 2022)