Designing ultra-low voltage PLL Using a bulk-driven technique. - Ting-Sheng Chao; Yu-Lung Lo; Wei-Bin Yang; Kuo-Hsing Cheng (ESSCIRC, 2009)

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. - Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng (IEICE Trans. Electron., 2009)

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. - Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output. - Wei-Bin Yang; Yu-Lung Lo; Ting-Sheng Chao (IEICE Trans. Electron., 2010)