A 84.7-DR wide BW incremental ADC using CT structure. - Ting-Yang Wang; Tai-Cheng Lee (VLSI-DAT, 2015)

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS. - Chan-Hsiang Weng; Tzu-An Wei; Hung-Yi Hsieh; Su-Hao Wu; Ting-Yang Wang (VLSI Circuits, 2019)