Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. - Tingjun Wen; Tadeusz Kwasniewski (BMAS, 2008)

A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS. - Yuriy M. Greshishchev; Tingjun Wen; Naim Ben-Hamida; Jorge Aguirre; Sadok Aouini; Marinette Besson; Robert Gibbins; Young Gouk Cho; Jerry Lam; Douglas McPherson; Mahdi Parvizi (BCICTS, 2019)