Multi-Level Logic Synthesis Using Communication Complexity. - TingTing Hwang; Robert Michael Owens; Mary Jane Irwin (DAC, 1989)

Logic synthesis for programmable logic devices. - TingTing Hwang; Robert Michael Owens; Mary Jane Irwin (ICCD, 1990)

Exploiting communication complexity for multilevel logic synthesis. - TingTing Hwang; Robert Michael Owens; Mary Jane Irwin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Performance-driven interconnection optimization for microarchitecture synthesis. - Yi-Min Jiang; Tsing-Fa Lee; TingTing Hwang; Yaun-Long Lin (EURO-DAC, 1992)

ELM-A Fast Addition Algorithm Discovered by a Program. - Thomas P. Kelliher; Robert Michael Owens; Mary Jane Irwin; TingTing Hwang (IEEE Trans. Computers, 1992)

Efficiently computing communication complexity for multilevel logic synthesis. - TingTing Hwang; Robert Michael Owens; Mary Jane Irwin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Combining technology mapping and placement for delay-optimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCAD, 1993)

Cell Height Driven Transistor Sizing in a Cell Based Module Design. - How-Rern Lin; Ching-Lung Chou; Yu-Chin Hsu; TingTing Hwang (EDAC-ETC-EUROASIC, 1994)

Dynamical identification of critical paths for iterative gate sizing. - How-Rern Lin; TingTing Hwang (ICCAD, 1994)

State Assignment for Power and Area Minimization. - Kuo-Hua Wang; Wen-Sing Wang; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCD, 1994)

Logic synthesis for field-programmable gate arrays. - TingTing Hwang; Robert Michael Owens; Mary Jane Irwin; Kuo-Hua Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Performance-driven interconnection optimization for microarchitecture synthesis. - Yi-Min Jiang; Tsing-Fa Lee; TingTing Hwang; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Technology Mapping for FPGA Using Generalized Functional Decomposition. - Kuo-Hua Wang; Cheng Chen; Ting Ting Hwang (VLSI Design, 1994)

Power recduction by gate sizing with path-oriented slack calculation. - How-Rern Lin; TingTing Hwang (ASP-DAC, 1995)

Combining technology mapping and placement for delay-minimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Layout Driven Selecting and Chaining of Partial Scan. - Chau-Shen Chen; Kuang-Hui Lin; TingTing Hwang (DAC, 1996)

Cell height driven transistor sizing in a cell based static CMOS module design. - How-Rern Lin; Yu-Chin Hsu; TingTing Hwang (IEEE J. Solid State Circuits, 1996)

Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. - Shih-Chieh Chang; Malgorzata Marek-Sadowska; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Exploiting communication complexity for Boolean matching. - Kuo-Hua Wang; TingTing Hwang; Cheng Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Low power realization of finite state machines - a decomposition approach. - Sue-Hong Chow; Yi-Cheng Ho; TingTing Hwang; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 1996)

Low Power FPGA Design - A Re-engineering Approach. - Chau-Shen Chen; TingTing Hwang; C. L. Liu 001 (DAC, 1997)

Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. - Shiuann-Shiuh Lin; Yuh-Ju Lin; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Boolean matching for incompletely specified functions. - Kuo-Hua Wang; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A Re-engineering Approach to Low Power FPGA Design Using SPFD. - Jan-Min Hwang; Feng-Yi Chiang; TingTing Hwang (DAC, 1998)

Layout Driven Selection and Chaining of Partial Scan Flip-Flops. - Chau-Shen Chen; TingTing Hwang (J. Electron. Test., 1998)

A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. - Shiuann-Shiuh Lin; Wen-Hsin Chen; Wen-Wei Lin; TingTing Hwang (ASP-DAC, 1999)

Logic Transformation for Low Power Synthesis. - Ki-Wook Kim; Sung-Mo Kang; TingTing Hwang; C. L. Liu 001 (DATE, 1999)

On determining sensitization criterion in an iterative gate sizing process. - How-Rern Lin; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Compiler Optimization on Instruction Scheduling for Low Power. - Chingren Lee; Jenq Kuen Lee; TingTing Hwang; Shi-Chun Tsai (ISSS, 2000)

A construction of minimal delay Steiner tree using two-pole delay model. - LiYi Lin; Yi-Yu Liu; TingTing Hwang (ASP-DAC, 2001)

Binary decision diagram with minimum expected path length. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang; C. L. Liu 001 (DATE, 2001)

Architecture driven circuit partitioning. - Chau-Shen Chen; TingTing Hwang; C. L. Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A technology mapping algorithm for CPLD architectures. - Shih-Liang Chen; TingTing Hwang; C. L. Liu 001 (FPT, 2002)

Instruction buffering for nested loops in low power design. - Chi Ta Wu; TingTing Hwang (ISCAS (4), 2002)

Logic transformation for low-power synthesis. - Ki-Wook Kim; Taewhan Kim 001; TingTing Hwang; Sung-Mo Kang; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 2002)

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. - Alex C.-Y. Chang; Wu-An Kuo; Allen C.-H. Wu; TingTing Hwang (DATE, 2003)

Decomposition of Extended Finite State Machine for Low Power Design. - MingHung Lee; TingTing Hwang; Shi-Yu Huang (DATE, 2003)

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. - Jennifer Y.-L. Lo; Wu-An Kuo; Allen C.-H. Wu; TingTing Hwang (DATE, 2003)

Compiler optimization on VLIW instruction scheduling for low power. - Chingren Lee; Jenq Kuen Lee; TingTing Hwang; Shi-Chun Tsai (ACM Trans. Design Autom. Electr. Syst., 2003)

Low power design using dual threshold voltage. - Yen-Te Ho; TingTing Hwang (ASP-DAC, 2004)

Decomposition of Instruction Decoder for Low Power Design. - Wu-An Kuo; TingTing Hwang; Allen C.-H. Wu (DATE, 2004)

Crosstalk Minimization in Logic Synthesis for PLA. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang (DATE, 2004)

Output-pattern directed decomposition for low power design. - Chi-Wei Hu; TingTing Hwang (ISCAS (5), 2004)

Power-Aware Scheduling for Parallel Security Processors with Analytical Models. - Yung-Chia Lin; Yi-Ping You; Chung-Wen Huang; Jenq Kuen Lee; Wei-Kuan Shih; TingTing Hwang (LCPC, 2004)

Functionality directed clustering for low power MTCMOS design. - Tsuang-Wei Chang; TingTing Hwang; Sheng-Yu Hsu (ASP-DAC, 2005)

Low-power techniques for network security processors. - Yi-Ping You; Chun-Yen Tseng; Yu-Hui Huang; Po-Chiun Huang; TingTing Hwang; Sheng-Yu Hsu (ASP-DAC, 2005)

Switching-activity driven gate sizing and Vth assignment for low power design. - Yu-Hui Huang; Po-Yuan Chen; TingTing Hwang (ASP-DAC, 2006)

A bus architecture for crosstalk elimination in high performance processor design. - Wen-Wen Hsieh; Po-Yuan Chen; TingTing Hwang (CODES+ISSS, 2006)

Performance-driven crosstalk elimination at post-compiler level. - Wu-An Kuo; Yi-Ling Chiang; TingTing Hwang; Allen C.-H. Wu (ISCAS, 2006)

Decomposition of instruction decoders for low-power designs. - Wu-An Kuo; TingTing Hwang; Allen C.-H. Wu (ACM Trans. Design Autom. Electr. Syst., 2006)

Crosstalk minimization in logic synthesis for PLAs. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2006)

A power-driven multiplication instruction-set design method for ASIPs. - Wu-An Kuo; TingTing Hwang; Allen C.-H. Wu (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Instruction buffering for nested loops in low-power design. - Chi Ta Wu; Ang-Chih Hsieh; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. - Wen-Wen Hsieh; Po-Yuan Chen; Chun-Yao Wang; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. - Wu-An Kuo; Yi-Ling Chiang; TingTing Hwang; Allen C.-H. Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Crosstalk-Aware Domino-Logic Synthesis. - Yi-Yu Liu; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. - Yung-Chia Lin; Yi-Ping You; Chung-Wen Huang; Jenq Kuen Lee; Wei-Kuan Shih; TingTing Hwang (J. Supercomput., 2007)

A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. - Ang-Chih Hsieh; Tzu-Teng Lin; Tsuang-Wei Chang; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2007)

Transition-aware decoupling-capacitor allocation in power noise reduction. - Po-Yuan Chen; Che-Yu Liu; TingTing Hwang (ICCAD, 2008)

Digital Secure-Communication Using Robust Hyper-Chaotic Systems. - Shih-Liang Chen; Shu-Ming Chang; Wen-Wei Lin; TingTing Hwang (Int. J. Bifurc. Chaos, 2008)

Synthesis of a novel timing-error detection architecture. - Yu-Shih Su; Po-Hsien Chang; Shih-Chieh Chang; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2008)

Thermal-aware post compilation for VLIW architectures. - Wen-Wen Hsieh; TingTing Hwang (ASP-DAC, 2009)

New spare cell design for IR drop minimization in Engineering Change Order. - Hsien-Te Chen; Chieh-Chun Chang; TingTing Hwang (DAC, 2009)

A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. - Wen-Wen Hsieh; I-Sheng Lin; TingTing Hwang (DATE, 2009)

Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. - Po-Yuan Chen; Chiao-Chen Fang; TingTing Hwang; Hsi-Pin Ma (ACM Trans. Design Autom. Electr. Syst., 2009)

Skew-aware polarity assignment in clock tree. - Po-Yuan Chen; Kuan-Hsien Ho; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2009)

TSV redundancy: Architecture and design issues in 3D IC. - Ang-Chih Hsieh; TingTing Hwang; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Hung-Chun Li (DATE, 2010)

A Fast Digital Chaotic Generator for Secure Communication. - Shih-Liang Chen; TingTing Hwang; Shu-Ming Chang; Wen-Wei Lin (Int. J. Bifurc. Chaos, 2010)

A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. - Wen-Wen Hsieh; Shih-Liang Chen; I-Sheng Lin; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Randomness Enhancement Using Digitalized Modified Logistic Map. - Shih-Liang Chen; TingTing Hwang; Wen-Wei Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. - Hsien-Te Chen; Chieh-Chun Chang; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A physical-location-aware fault redistribution for maximum IR-drop reduction. - Fu-Wei Chen; Shih-Liang Chen; Yung-Sheng Lin; TingTing Hwang (ASP-DAC, 2011)

Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. - Ang-Chih Hsieh; Chun-Cheng Liu; TingTing Hwang (ASP-DAC, 2011)

A new architecture for power network in 3D IC. - Hsien-Te Chen; Hong-Long Lin; Zi-Cheng Wang; TingTing Hwang (DATE, 2011)

Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. - Ang-Chih Hsieh; Yi-Ta Wu; Shau-Yin Tseng; TingTing Hwang (ICPP, 2011)

Through-Silicon Via Planning in 3-D Floorplanning. - Ming-Chao Tsai; Ting-Chi Wang; Ting Ting Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Clock tree synthesis with methodology of re-use in 3D IC. - Fu-Wei Chen; TingTing Hwang (DAC, 2012)

A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. - Fu-Wei Chen; Shih-Liang Chen; Yung-Sheng Lin; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

TSV Redundancy: Architecture and Design Issues in 3-D IC. - Ang-Chih Hsieh; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Run-Time Reconfiguration of Expandable Cache for Embedded Systems. - Ang-Chih Hsieh; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Stacking signal TSV for thermal dissipation in global routing for 3D IC. - Po-Yang Hsu; Hsien-Te Chen; TingTing Hwang (ASP-DAC, 2013)

Thread-criticality aware dynamic cache reconfiguration in multi-core system. - Po-Yang Hsu; TingTing Hwang (ICCAD, 2013)

Thermal-aware memory mapping in 3D designs. - Ang-Chih Hsieh; TingTing Hwang (ACM Trans. Embed. Comput. Syst., 2013)

Fault-tolerant TSV by using scan-chain test TSV. - Fu-Wei Chen; Hui-Ling Ting; TingTing Hwang (ASP-DAC, 2014)

Compaction-free compressed cache for high performance multi-core system. - Po-Yang Hsu; Pei-Lan Lin; TingTing Hwang (ICCAD, 2014)

Clock-Tree Synthesis with Methodology of Reuse in 3D-IC. - Fu-Wei Chen; TingTing Hwang (ACM J. Emerg. Technol. Comput. Syst., 2014)

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC. - Po-Yang Hsu; Hsien-Te Chen; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Utilizing Circuit Structure for Scan Chain Diagnosis. - Wei-Hen Lo; Ang-Chih Hsieh; Chien-Ming Lan; Min-Hsien Lin; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. - Yen-Hao Chen; Yi-Lun Tang; Yi-Yu Liu; Allen C.-H. Wu; TingTing Hwang (DATE, 2016)

Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). - Wei-Hen Lo; Kai-zen Liang; TingTing Hwang (DATE, 2016)

Architecture of Ring-Based Redundant TSV for Clustered Faults. - Wei-Hen Lo; Kang Chi; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs. - Chia-Ling Chen; Yen-Hao Chen; TingTing Hwang (ASP-DAC, 2017)

Architectural evaluations on TSV redundancy for reliability enhancement. - Yen-Hao Chen; Chien-Pang Chiu; Russell Barnes; TingTing Hwang (DATE, 2017)

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. - Yen-Hao Chen; Yi-Lun Tang; Yi-Yu Liu; Allen C.-H. Wu; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Crosstalk-aware TSV-buffer Insertion in 3D IC. - Yen-Hao Chen; Po-Chen Huang; Fu-Wei Chen; Allen C.-H. Wu; TingTing Hwang (SoCC, 2019)

Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. - Pei-An Ho; Yen-Hao Chen; Allen C.-H. Wu; TingTing Hwang (SoCC, 2019)

A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. - Chin-Yu Sun; Allen C.-H. Wu; TingTing Hwang (CoRR, 2019)

A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). - Yen-Hao Chen; Allen C.-H. Wu; TingTing Hwang (ASP-DAC, 2021)

A novel privacy-preserving deep learning scheme without a cryptography component. - Chin-Yu Sun; Allen C.-H. Wu; TingTing Hwang (Comput. Electr. Eng., 2021)

A New Attack for Self-Certified Digital Signatures for E-commerce Applications. - Chin-Yu Sun; Hsiao-Ling Wu; Hung-Min Sun; TingTing Hwang (J. Inf. Sci. Eng., 2021)

Expanding In-Cone Obfuscated Tree for Anti SAT Attack. - RuiJie Wang; Li-Nung Hsu; Yung-Chih Chen; TingTing Hwang (DATE, 2023)

M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties. - Yuan-Tai Lin; Chin-Yu Sun; TingTing Hwang (SOCC, 2023)

A Hybrid Approach to Reverse Engineering on Combinational Circuits. - Wuqian Tang; Yi-Ting Li; Kai-Po Hsu; Kuan-Ling Chou; You-Cheng Lin; Chia-Feng Chien; Tzu-Li Hsu; Yung-Chih Chen; Ting-Chi Wang; Shih-Chieh Chang; TingTing Hwang; Chun-Yao Wang (DATE, 2024)

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. - Cheng-Hsien Lin; Kuan-Ting Chen; Yi-Yu Liu; Allen C.-H. Wu; Tingting Hwang (ACM Trans. Design Autom. Electr. Syst., 2024)

Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC Locking. - Hsiang-Chun Cheng; RuiJie Wang; TingTing Hwang (DATE, 2025)