A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. - Chang Liu; Bozhi Yin; Tingyu Yao; Nan Qi; Dan Li 011; Jingbo Shi; Juncheng Wang; Hu Shang; Rui Bai 001; Patrick Yin Chiang (OFC, 2018)

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. - Shang Hu; Tingyu Yao; Bozhi Yin; Chunyu Song; Lei Zhao; Juncheng Wang; Lei Wang 187; Rui Bai 001; Xin Wang 130; Tao Xia; Yi Peng; Binbin Yao; et al. (OFC, 2019)