PAAS: A system level simulator for heterogeneous computing architectures. - Tingyuan Liang; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (FPL, 2017)

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. - Tingyuan Liang; Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. - Liang Feng 001; Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (DAC, 2019)

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. - Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (DATE, 2019)

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. - Liang Feng 001; Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (FPGA, 2019)

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. - Tingyuan Liang; Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (ICCAD, 2019)

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. - Jieru Zhao; Tingyuan Liang; Liang Feng 001; Wenchao Ding 001; Sharad Sinha; Wei Zhang 012; Shaojie Shen (FPL, 2020)

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ICCAD, 2021)

AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining. - Tingyuan Liang; Jingsong Chen; Lei Li; Wei Zhang 012 (CoRR, 2022)

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. - Jian Peng; Tingyuan Liang; Zhiyao Xie; Wei Zhang 012 (DAC, 2023)

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Sharad Sinha; Zhiyao Xie; Wei Zhang 012 (FPGA, 2023)

DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. - Liangji Chen; Tingyuan Liang; Wei Zhang 012; Sharad Sinha (ICFPT, 2023)

MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network. - Weihua Xiao; Shanshan Han; Yue Yang; Shaoze Yang; Cheng Zheng; Jingsong Chen; Tingyuan Liang; Lei Li; Weikang Qian (ICCAD, 2023)

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. - Zhe Lin 007; Tingyuan Liang; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration. - Hanwei Fan; Ya Wang; Sicheng Li 001; Tingyuan Liang; Wei Zhang 012 (DAC, 2024)

A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration. - Ya Wang; Hanwei Fan; Sicheng Li 001; Tingyuan Liang; Wei Zhang 012 (DATE, 2024)

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. - Chunyou Su; Linfeng Du; Tingyuan Liang; Zhe Lin 007; Maolin Wang 002; Sharad Sinha; Wei Zhang 012 (FPGA, 2024)

AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Xiaofeng Zhou; Jinming Ge; Shangkun Li; Sharad Sinha; Jieru Zhao; Zhiyao Xie; Wei Zhang 012 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. - Jian Peng; Tingyuan Liang; Jingbo Jiang; Yipu Zhang; Zhe Lin 007; Zhiyao Xie; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)