Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures. - Titu Mary Ignatius; Satyajit Bora; Roy Paily Palathinkal (MCSoC, 2024)

Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications. - Titu Mary Ignatius; Thockchom Birjit Singha; Roy Paily Palathinkal (IEEE Access, 2024)

Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks. - Thockchom Birjit Singha; Basa Sanjana; Titu Mary Ignatius; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Trans. Very Large Scale Integr. Syst., 2024)

RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience. - Nayana Rajeev; Cathrene Biju; Titu Mary Ignatius; Roy Paily Palathinkal; Rekha K. James (IEEE Comput. Archit. Lett., 2025)

Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks. - Vishnu Padmakumar; Titu Mary Ignatius; Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Embed. Syst. Lett., 2025)