A dynamic time warp IC for a one thousand word recognition system. - Robert Kavaler; Robert W. Brodersen; Tobias G. Noll; Menahem Lowy; Hy Murveit (ICASSP, 1984)

MOS-VLSI pipelined digital filters for video applications. - Walter Ulbrich; Tobias G. Noll; B. Zehner (ICASSP, 1984)

VLSI architectures for the full-search blockmatching algorithm. - Luc de Vos; M. Stegherr; Tobias G. Noll (ICASSP, 1989)

CMOS VLSI implementation of the 2D-DCT with linear processor arrays. - U. Totzek; F. Matthiesen; S. Wohlleben; Tobias G. Noll (ICASSP, 1990)

Carry-save architectures for high-speed digital signal processing. - Tobias G. Noll (J. VLSI Signal Process., 1991)

Low Power CMOS Design Strategies. - Matthias Schöbinger; Tobias G. Noll (DAC, 1994)

A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators. - Erik De Man; Matthias Schöbinger; Tobias G. Noll; Georg Sebald (ISCAS, 1994)

Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications. - Erik De Man; Michael Schulz; Richard Schmidmaier; Matthias Schöbinger; Tobias G. Noll (IEEE J. Solid State Circuits, 1995)

A Flexible Motion Estimation Chip for Variable Size Block Matching. - Jan Peter Berns; Tobias G. Noll (ASAP, 1996)

Korrektur der Phasenaberration in Ultraschallaufnahmen durch das Dynamic-Time-Warping Verfahren. - K. Eck; Andreas R. Brenner; Tobias G. Noll (Bildverarbeitung für die Medizin, 1996)

Artefaktreduzierung in der ultraschnellen Magnetresonanz-Bildgebung mittels inverser Filterung im Ortsfrequenzbereich. - S. Kannengießer; Andreas R. Brenner; Tobias G. Noll (Bildverarbeitung für die Medizin, 1996)

A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. - Michael Gansen; Frank Richter; Oliver Weiss; Tobias G. Noll (ASAP, 1997)

A novel systematic mapping approach for highly efficient multiplexed FIR-filter architectures. - Wolfgang Wilhelm; Tobias G. Noll (ICASSP, 1997)

Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung. - K. Eck; Andreas R. Brenner; Wolfgang Wilhelm; Tobias G. Noll (Bildverarbeitung für die Medizin, 1998)

Tiefenangepaßte Filterung für das Puls-Echo-Verfahren in der Ultraschalldiagnostik. - Robert Schwann; K. Eck; Andreas R. Brenner; Tobias G. Noll (Bildverarbeitung für die Medizin, 1998)

Architecture and implementation of a bitserial sorter for weighted median filtering. - Christiane Henning; Tobias G. Noll (CICC, 1998)

A new scalable VLSI architecture for Reed-Solomon decoders. - Wolfgang Wilhelm; A. Kaufmann; Tobias G. Noll (CICC, 1998)

A hybrid equalizer merging the advantages of Baud spaced and fractionally spaced equalizers. - Christian Lütkemeyer; Hans-Martin Blüthgen; Tobias G. Noll (ICASSP, 1998)

A transversal equalizer with an increased adaptation speed and tracking capability. - Christian Lütkemeyer; Tobias G. Noll (IEEE J. Solid State Circuits, 1998)

Device visualization for interventional MRI using local magnetic fields: Basic theory and its application to catheter visualization. - Arndt Glowinski; Jürgen Küsch; Gerhard Adam; Arno Bücker; Tobias G. Noll; Rolf W. Günther (IEEE Trans. Medical Imaging, 1998)

A Flexible 200 GOPS HDTV Motion Estimation Chip. - Jan Peter Berns; Tobias G. Noll (J. VLSI Signal Process., 1998)

A Programmable Processor for Approximate String Matching with High Throughput Rate. - Hans-Martin Blüthgen; Tobias G. Noll (ASAP, 2000)

A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. - V. S. Gierenz; Oliver Weiss; Tobias G. Noll; I. Carew; Jonathan J. Ashley; Razmik Karabed (ASAP, 2000)

A Hardware Implementation for Approximate Text Search in Multimedia Applications. - Hans-Martin Blüthgen; Patrick Osterloh; Holger Blume; Tobias G. Noll (IEEE International Conference on Multimedia and Expo (III), 2000)

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. - Holger Blume; H. Hübert; H. T. Feldkämper; Tobias G. Noll (ASAP, 2002)

Implementation of scalable power and area efficient high-throughput Viterbi decoders. - Tobias Gemmeke; Michael Gansen; Tobias G. Noll (IEEE J. Solid State Circuits, 2002)

Object based refinement of motion vector fields applying probabilistic homogenization rules. - Holger Blume; G. Herczeg; O. Erdler; Tobias G. Noll (IEEE Trans. Consumer Electron., 2002)

Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. - Holger Blume; Hans-Martin Blüthgen; Christiane Henning; Patrick Osterloh; Tobias G. Noll (J. VLSI Signal Process., 2002)

A physically oriented model to quantify the dynamic noise margin [on-chip noise]. - Tobias Gemmeke; Tobias G. Noll (ESSCIRC, 2004)

A Physically Oriented Model to Quantify the Noise-on-Delay Effect. - Tobias Gemmeke; Tobias G. Noll (PATMOS, 2004)

Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. - Holger Blume; Thorsten von Sydow; Tobias G. Noll (SAMOS, 2004)

Segmentation in the loop: an iterative object-based algorithm for motion estimation. - Holger Blume; Jörg von Livonius; Tobias G. Noll (VCIP, 2004)

Design optimization of low-power high-performance DSP building blocks. - Tobias Gemmeke; Michael Gansen; Heinrich J. Stockmanns; Tobias G. Noll (IEEE J. Solid State Circuits, 2004)

A parametrizable low-power high-throughput turbo-decoder. - Gordian Prescher; Tobias Gemmeke; Tobias G. Noll (ICASSP (5), 2005)

Error-tolerant FIR filters based on low-cost residue codes. - José L. Rodríguez-Navarro; Michael Gansen; Tobias G. Noll (ISCAS (5), 2005)

Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets. - Holger Blume; Thorsten von Sydow; Daniel Becker 001; Tobias G. Noll (SAMOS, 2005)

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. - Holger Blume; H. T. Feldkämper; Tobias G. Noll (J. VLSI Signal Process., 2005)

Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. - Friederich Kupzog; Holger Blume; Tobias G. Noll; Kieran McLaughlin; Sakir Sezer; John V. McCanny (AICT/ICIW, 2006)

Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. - Thorsten von Sydow; Bernd Neumann; Holger Blume; Tobias G. Noll (ASAP, 2006)

Application specific instruction processor based implementation of a GNSS receiver on an FPGA. - Götz Kappen; Tobias G. Noll (DATE Designers' Forum, 2006)

Cross disciplinary aspects (4G wireless special day). - Tobias G. Noll; Uwe Lambrette (DATE, 2006)

Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros. - Thorsten von Sydow; Matthias Korb; Bernd Neumann; Holger Blume; Tobias G. Noll (ReConFig, 2006)

Hybrid Functional and Instruction Level Power Modeling for Embedded Processors. - Holger Blume; Daniel Becker 001; Martin Botteck; Jörg Brakensiek; Tobias G. Noll (SAMOS, 2006)

A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain. - Holger Blume; Thorsten von Sydow; Tobias G. Noll (J. VLSI Signal Process., 2006)

Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. - Götz Kappen; S. el Bahri; O. Priebe; Tobias G. Noll (ASAP, 2007)

Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory. - Alexander Flocke; Tobias G. Noll (ESSCIRC, 2007)

A Power Estimation Model for an FPGA-based Softcore Processor. - Peter Zipf; Heiko Hinkelmann; Lei Deng; Manfred Glesner; Holger Blume; Tobias G. Noll (FPL, 2007)

Programmable Architectures for Realtime Music Decompression. - Martin Botteck; Holger Blume; Jörg von Livonius; Martin Neuenhahn; Tobias G. Noll (PARCO, 2007)

Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. - Holger Blume; Jörg von Livonius; Lisa Rotenberg; Tobias G. Noll; Harald Bothe; Jörg Brakensiek (ICSAMOS, 2007)

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. - Holger Blume; Daniel Becker 001; Lisa Rotenberg; Martin Botteck; Jörg Brakensiek; Tobias G. Noll (J. Syst. Archit., 2007)

Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures. - Holger Blume; Thorsten von Sydow; Daniel Becker 001; Tobias G. Noll (J. Syst. Archit., 2007)

Design flow for embedded FPGAs based on a flexible architecture template. - Bernd Neumann; Thorsten von Sydow; Holger Blume; Tobias G. Noll (DATE, 2008)

Application-specific reconfigurable processors. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner; Matthias Alles; Timo Vogt; Norbert Wehn; Götz Kappen; Tobias G. Noll (FPL, 2008)

Adaptive kernel algorithm for FPGA-based speckle reduction. - Gerhard Tech; Robert Schwann; Götz Kappen; Michael Först; Tobias G. Noll (Image Processing, 2008)

Design of a Pareto-optimization environment and its application to motion estimation. - Jörg von Livonius; Holger Blume; Tobias G. Noll (MMSP, 2008)

ASIP-eFPGA Architecture for Multioperable GNSS Receivers. - Thorsten von Sydow; Holger Blume; Götz Kappen; Tobias G. Noll (SAMOS, 2008)

OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis. - Holger Blume; Jörg von Livonius; Lisa Rotenberg; Tobias G. Noll; Harald Bothe; Jörg Brakensiek (J. Syst. Archit., 2008)

A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. - Kieran McLaughlin; Sakir Sezer; Holger Blume; Xin Yang 010; Friederich Kupzog; Tobias G. Noll (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. - Bernd Neumann; Thorsten von Sydow; Holger Blume; Tobias G. Noll (J. Signal Process. Syst., 2008)

Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures. - Matthias Korb; Tobias G. Noll (ESSCIRC, 2009)

Reconfigurable Components for Application-Specific Processor Architectures. - Tobias G. Noll; Thorsten von Sydow; Bernd Neumann; Jochen Schleifer; Thomas Coenen; Götz Kappen (Dynamically Reconfigurable Systems, 2010)

Potential of using block floating point arithmetic in ASIP-based GNSS-receivers. - Emrah Tasdemir; Götz Kappen; Tobias G. Noll (ASAP, 2010)

A radix-4 single-precision floating point divider based on digit set interleaving. - Ingo Rust; Tobias G. Noll (ISCAS, 2010)

Interconnect routing of embedded FPGAs using standard VLSI routing tools. - Thomas Coenen; Jochen Schleifer; Oliver Weiß; Tobias G. Noll (SoC, 2010)

LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates. - Matthias Korb; Tobias G. Noll (SoC, 2010)

A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point. - Ingo Rust; Tobias G. Noll (SoC, 2010)

MATLAB Meets LEGO Mindstorms - A Freshman Introduction Course Into Practical Engineering. - Alexander Behrens; Linus Atorf; Robert Schwann; Bernd Neumann; Rainer Schnitzler; Johannes Ballé; Thomas Herold; Aulis Telle; Tobias G. Noll; Kay Hameyer; Til Aach (IEEE Trans. Educ., 2010)

Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers. - Götz Kappen; Lothor Kurz; O. Priebe; Tobias G. Noll (J. Signal Process. Syst., 2010)

Area- and energy-efficient high-throughput LDPC decoders with low block latency. - Matthias Korb; Tobias G. Noll (ESSCIRC, 2011)

Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization. - Arne Heittmann; Tobias G. Noll (ACM Great Lakes Symposium on VLSI, 2011)

Statistical modeling of reliability in logic devices. - Jochen Schleifer; Thomas Coenen; Tobias G. Noll (Microelectron. Reliab., 2011)

A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights. - Arne Heittmann; Tobias G. Noll (ESANN, 2012)

Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits. - Arne Heittmann; Tobias G. Noll (ACM Great Lakes Symposium on VLSI, 2012)

Efficient VLSI architectures of QPP interleavers for LTE turbo decoders. - Martin Broich; Tobias G. Noll (ISSoC, 2012)

A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars. - Arne Heittmann; Tobias G. Noll (NANOARCH, 2012)

Noise Margin Based Library Optimization Considering Variability in Sub-threshold. - Tobias Gemmeke; Maryam Ashouei; Tobias G. Noll (PATMOS, 2012)

A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations. - Matthias Korb; Tobias G. Noll (ICSAMOS, 2012)

Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme. - Yuan Ren; Michael Gansen; Tobias G. Noll (SoCC, 2012)

An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks. - Upasna Vishnoi; Michael Meixner; Tobias G. Noll (SoCC, 2012)

Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation. - Arne Heittmann; Tobias G. Noll (ASP-DAC, 2013)

High-level modeling and synthesis for embedded FPGAs. - Xiaolin Chen; Shuai Li; Jochen Schleifer; Thomas Coenen; Anupam Chattopadhyay; Gerd Ascheid; Tobias G. Noll (DATE, 2013)

Cross-layer optimization of QRD accelerators. - Upasna Vishnoi; Tobias G. Noll (ESSCIRC, 2013)

Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits. - Arne Heittmann; Tobias G. Noll (ACM Great Lakes Symposium on VLSI, 2013)

Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays. - Qin Wang; Arne Heittmann; Tobias G. Noll (ACM Great Lakes Symposium on VLSI, 2013)

A family of modular area- and energy-efficient QRD-accelerator architectures. - Upasna Vishnoi; Tobias G. Noll (ISSoC, 2013)

An accurate power estimation model for low-power hierarchical-architecture SRAMs. - Yuan Ren; Tobias G. Noll (VLSI-SoC, 2013)

Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models. - Yuan Ren; Tobias G. Noll (VLSI-SoC (Selected Papers), 2013)

Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit. - Arne Heittmann; Tobias G. Noll (ISCAS, 2014)

Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders. - Martin Broich; Tobias G. Noll (ISSoC, 2014)

Limits of gate-level power estimation considering real delay effects and glitches. - Michael Meixner; Tobias G. Noll (ISSoC, 2014)

Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption. - Michael Meixner; Tobias G. Noll (VLSID, 2014)

On the use of analytical techniques for reliability analysis in presence of hardware-induced errors. - Georgia Psychou; Tobias Gemmeke; Tobias G. Noll (INDIN, 2015)

Design and synthesis of reconfigurable control-flow structures for CGRA. - Zoltán Endre Rákossy; Axel Acosta-Aponte; Tobias G. Noll; Gerd Ascheid; Rainer Leupers; Anupam Chattopadhyay (ReConFig, 2015)

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations. - Dimitrios Rodopoulos; Georgia Psychou; Mohamed M. Sabry; Francky Catthoor; Antonis Papanikolaou; Dimitrios Soudris; Tobias G. Noll; David Atienza (ACM Comput. Surv., 2015)

A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects. - Georgia Psychou; Tobias Gemmeke; Tobias G. Noll (PATMOS, 2016)

A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency. - Upasna Vishnoi; Michael Meixner; Tobias G. Noll (J. Signal Process. Syst., 2016)

Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells. - Arne Heittmann; Tobias G. Noll (NANOARCH, 2017)

Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems. - Georgia Psychou; Dimitrios Rodopoulos; Mohamed M. Sabry; Tobias Gemmeke; David Atienza; Tobias G. Noll; Francky Catthoor (ACM Comput. Surv., 2017)

Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup. - Michael Meixner; Tobias G. Noll (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency. - Martin Broich; Tobias G. Noll (J. Signal Process. Syst., 2017)

Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells. - Arne Heittmann; Tobias G. Noll (DATE, 2018)