Basic Architecture for Logic Self Repair. - Tobias Koal; Heinrich Theodor Vierhaus (IOLTS, 2008)

A scheme of logic self repair including local interconnects. - Tobias Koal; Daniel Scheit; Heinrich Theodor Vierhaus (DDECS, 2009)

Reliability Estimation Process. - Tobias Koal; Daniel Scheit; Heinrich Theodor Vierhaus (DSD, 2009)

A Concept for Logic Self Repair. - Tobias Koal; Heinrich Theodor Vierhaus; Daniel Scheit (DSD, 2009)

A software-based self-test and hardware reconfiguration solution for VLIW processors. - Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2010)

Combining de-stressing and self repair for long-term dependable systems. - Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2010)

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. - Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2011)

A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. - Markus Ulbricht 002; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2011)

On the Feasibility of Built-In Self Repair for Logic Circuits. - Tobias Koal; Daniel Scheit; Mario Schölzel; Heinrich Theodor Vierhaus (DFT, 2011)

Combining on-line fault detection and logic self repair. - Tobias Koal; Markus Ulbricht 002; Heinrich Theodor Vierhaus (DDECS, 2012)

An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. - Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2012)

Activity Migration in M-of-N-Systems by Means of Load-Balancing. - Markus Ulbricht 002; Heinrich Theodor Vierhaus; Tobias Koal (DSD, 2012)

On the feasibility of combining on-line-test and self repair for logic circuits. - Tobias Koal; Markus Ulbricht 002; Piet Engelke; Heinrich Theodor Vierhaus (DDECS, 2013)

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. - Petr Pfeifer; Zdenek Plíva; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2013)

Virtual TMR Schemes Combining Fault Tolerance and Self Repair. - Tobias Koal; Markus Ulbricht 002; Heinrich Theodor Vierhaus (DSD, 2013)

Towards an automatic generation of diagnostic in-field SBST for processor components. - Mario Schölzel; Tobias Koal; Stephanie Roder; Heinrich Theodor Vierhaus (LATW, 2013)

Combining fault tolerance and self repair at minimum cost in power and hardware. - Tobias Koal; Mario Schölzel; Heinrich Theodor Vierhaus (DDECS, 2014)

Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults. - Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DFT, 2014)

Reconfigurable high performance architectures: How much are they ready for safety-critical applications? - Davide Sabena; Luca Sterpone; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus; S. Wong; Robért Glein; Florian Rittner; C. Stender; Mario Porrmann; Jens Hagemeyer (ETS, 2014)

Systematic generation of diagnostic software-based self-test routines for processor components. - Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (ETS, 2014)

Timing for virtual TMR in logic circuits. - Sebastian Müller 005; Tobias Koal; Mario Schölzel; Heinrich Theodor Vierhaus (IOLTS, 2014)

Effiziente Auswahl redundanter Komponenten für Prozessoren zur Kompensation permanenter Fehler. - Tobias Koal (2014)

Redundancy evaluation process of processor components for permanent fault compensation. - Tobias Koal; Heinrich Theodor Vierhaus (AHS, 2015)

Combining Correction of Delay Faults and Transient Faults. - Tobias Koal; Stefan Scharoba; Heinrich Theodor Vierhaus (DDECS, 2015)

A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. - Sebastian Müller 005; Tobias Koal; Stefan Scharoba; Heinrich Theodor Vierhaus; Mario Schölzel (LATS, 2015)

A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. - Mario Schölzel; Tobias Koal; Sebastian Müller 005; Stefan Scharoba; Stephanie Roder; Heinrich Theodor Vierhaus (LATS, 2016)