7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. - John Davis; Paul Bunce; Diana M. Henderson; Yuen H. Chan; Uma Srinivasan 002; Daniel Rodko; Pradip Patel; Thomas J. Knips; Tobias Werner 001 (ISSCC, 2013)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors. - David Wolpert 001; Erwin Behnen; Leon J. Sigal; Yuen H. Chan; Gustavo Enrique Téllez; Douglas Bradley; Richard E. Serton; Rajesh Veerabhadraiah; William Ansley; Andrew Bianchi; Nagu Dhanwada; Sungjae Lee; et al. (IBM J. Res. Dev., 2018)

BonnCell: Automatic Cell Layout in the 7-nm Era. - Pascal Van Cleeff; Stefan Hougardy; Jannik Silvanus; Tobias Werner 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability. - David Wolpert 001; Gerry Strevig; Christopher J. Berry; Leon J. Sigal; Bill Huott; Mark Cichanowski; Matthias Pflanz; Tobias Werner 001; Philipp Salz; Nick Jinq; Michael Romain; Iris Leefken; et al. (ISSCC, 2025)