Dynamic Dependency Analysis of Ordinary Programs. - Todd M. Austin; Gurindar S. Sohi (ISCA, 1992)

Efficient Detection of All Pointer and Array Access Errors. - Todd M. Austin; Scott E. Breach; Gurindar S. Sohi (PLDI, 1994)

Streamlining Data Cache Access with Fast Address Calculation. - Todd M. Austin; Dionisios N. Pnevmatikatos; Gurindar S. Sohi (ISCA, 1995)

Zero-cycle loads: microarchitecture support for reducing load latency. - Todd M. Austin; Gurindar S. Sohi (MICRO, 1995)

Hardware and software mechanisms for reducing load latency. - Todd M. Austin (1996)

High-Bandwidth Address Translation for Multiple-Issue Processors. - Todd M. Austin; Gurindar S. Sohi (ISCA, 1996)

On High-Bandwidth Data Cache Design for Multi-Issue Processors. - Jude A. Rivers; Gary S. Tyson; Edward S. Davidson; Todd M. Austin (MICRO, 1997)

Improving the Accuracy and Performance of Memory Communication Through Renaming. - Gary S. Tyson; Todd M. Austin (MICRO, 1997)

The SimpleScalar tool set, version 2.0. - Doug Burger; Todd M. Austin (SIGARCH Comput. Archit. News, 1997)

Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures. - Artur Klauser; Todd M. Austin; Dirk Grunwald; Brad Calder (IEEE PACT, 1998)

Cache-Conscious Data Placement. - Brad Calder; Chandra Krintz; Simmi John; Todd M. Austin (ASPLOS, 1998)

The SimpleScalar tool set as an instructional tool: experiences and future directions. - Todd M. Austin (WCAE@HPCA, 1998)

Classifying load and store instructions for memory renaming. - Glenn Reinman; Brad Calder; Dean M. Tullsen; Gary S. Tyson; Todd M. Austin (International Conference on Supercomputing, 1999)

A Scalable Front-End Architecture for Fast Instruction Delivery. - Glenn Reinman; Todd M. Austin; Brad Calder (ISCA, 1999)

DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. - Todd M. Austin (MICRO, 1999)

Fetch Directed Instruction Prefetching. - Glenn Reinman; Brad Calder; Todd M. Austin (MICRO, 1999)

Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. - Gary S. Tyson; Todd M. Austin (Int. J. Parallel Program., 1999)

Challenges in processor modeling and validation [Guest Editors?? introduction]. - Pradip Bose; Thomas M. Conte; Todd M. Austin (IEEE Micro, 1999)

Architectural Support for Fast Symmetric-Key Cryptography. - Jerome Burke; John McDonald; Todd M. Austin (ASPLOS, 2000)

Efficient checker processor design. - Saugata Chatterjee; Christopher T. Weaver; Todd M. Austin (MICRO, 2000)

Compiler controlled value prediction using branch predictor based confidence. - Eric Larson; Todd M. Austin (MICRO, 2000)

DIVA: A Dynamic Approach to Microprocessor Verification. - Todd M. Austin (J. Instr. Level Parallelism, 2000)

Application specific architectures: a recipe for fast, flexible and power efficient designs. - Christopher T. Weaver; Rajeev Krishna; Lisa Wu 001; Todd M. Austin (CASES, 2001)

Scalable Hybrid Verification of Complex Microprocessors. - Maher N. Mneimneh; Fadi A. Aloul; Christopher T. Weaver; Saugata Chatterjee; Karem A. Sakallah; Todd M. Austin (DAC, 2001)

A Fault Tolerant Approach to Microprocessor Design. - Christopher T. Weaver; Todd M. Austin (DSN, 2001)

CryptoManiac: a fast flexible architecture for secure communication. - Lisa Wu 001; Christopher T. Weaver; Todd M. Austin (ISCA, 2001)

MASE: a novel infrastructure for detailed microarchitectural modeling. - Eric Larson; Saugata Chatterjee; Todd M. Austin (ISPASS, 2001)

Performance analysis using pipeline visualization. - Christopher T. Weaver; Kenneth C. Barr; Eric D. Marsman; Dan Ernst; Todd M. Austin (ISPASS, 2001)

Design for Verification? - Todd M. Austin (IEEE Des. Test Comput., 2001)

Optimizations Enabled by a Decoupled Front-End Architecture. - Glenn Reinman; Brad Calder; Todd M. Austin (IEEE Trans. Computers, 2001)

Efficient Dynamic Scheduling Through Tag Elimination. - Dan Ernst; Todd M. Austin (ISCA, 2002)

High Performance and Energy Efficient Serial Prefetch Architecture. - Glenn Reinman; Brad Calder; Todd M. Austin (ISHPC, 2002)

Effective support of simulation in computer architecture instruction. - Christopher T. Weaver; Eric Larson; Todd M. Austin (WCAE, 2002)

SimpleScalar: An Infrastructure for Computer System Modeling. - Todd M. Austin; Eric Larson; Dan Ernst (Computer, 2002)

Performance Simulation Tools. - Shubhendu S. Mukherjee; Sarita V. Adve; Todd M. Austin; Joel S. Emer; Peter S. Magnusson (Computer, 2002)

Architectural optimizations for low-power, real-time speech recognition. - Rajeev Krishna; Scott A. Mahlke; Todd M. Austin (CASES, 2003)

Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. - Dan Ernst; Andrew Hamel; Todd M. Austin (ISCA, 2003)

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. - Dan Ernst; Nam Sung Kim; Shidhartha Das; Sanjay Pant; Rajeev R. Rao; Toan Pham; Conrad H. Ziesler; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge (MICRO, 2003)

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. - Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin (MICRO, 2003)

High Coverage Detection of Input-Related Security Faults. - Eric Larson; Todd M. Austin (USENIX Security Symposium, 2003)

Leakage Current: Moore's Law Meets Static Power. - Nam Sung Kim; Todd M. Austin; David T. Blaauw; Trevor N. Mudge; Krisztián Flautner; Jie S. Hu; Mary Jane Irwin; Mahmut T. Kandemir; Narayanan Vijaykrishnan (Computer, 2003)

Measuring Architectural Vulnerability Factors. - Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin (IEEE Micro, 2003)

Memory system design space exploration for low-power, real-time speech recognition. - Rajeev Krishna; Scott A. Mahlke; Todd M. Austin (CODES+ISSS, 2004)

Designing robust microarchitectures. - Todd M. Austin (DAC, 2004)

Circuit-aware architectural simulation. - Seokwoo Lee; Shidhartha Das; Valeria Bertacco; Todd M. Austin; David T. Blaauw; Trevor N. Mudge (DAC, 2004)

Microarchitectural power modeling techniques for deep sub-micron microprocessors. - Nam Sung Kim; Taeho Kgil; Valeria Bertacco; Todd M. Austin; Trevor N. Mudge (ISLPED, 2004)

Reducing pipeline energy demands with local DVS and dynamic retiming. - Seokwoo Lee; Shidhartha Das; Toan Pham; Todd M. Austin; David T. Blaauw; Trevor N. Mudge (ISLPED, 2004)

Making Typical Silicon Matter with Razor. - Todd M. Austin; David T. Blaauw; Trevor N. Mudge; Krisztián Flautner (Computer, 2004)

Mobile Supercomputers. - Todd M. Austin; David T. Blaauw; Scott A. Mahlke; Trevor N. Mudge; Chaitali Chakrabarti; Wayne H. Wolf (Computer, 2004)

Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. - Dan Ernst; Shidhartha Das; Seokwoo Lee; David T. Blaauw; Todd M. Austin; Trevor N. Mudge; Nam Sung Kim; Krisztián Flautner (IEEE Micro, 2004)

Recent extensions to the SimpleScalar tool suite. - Doug Burger; Todd M. Austin; Stephen W. Keckler (SIGMETRICS Perform. Evaluation Rev., 2004)

Opportunities and challenges for better than worst-case design. - Todd M. Austin; Valeria Bertacco; David T. Blaauw; Trevor N. Mudge (ASP-DAC, 2005)

A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. - Leyla Nazhandali; Michael Minuth; Bo Zhai; Javin Olson; Todd M. Austin; David T. Blaauw (CASES, 2005)

StressTest: an automatic approach to test generation via activity monitors. - Ilya Wagner; Valeria Bertacco; Todd M. Austin (DAC, 2005)

DVS for On-Chip Bus Designs Based on Timing Error Correction. - Himanshu Kaul; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge; Todd M. Austin (DATE, 2005)

Deployment of Better Than Worst-Case Design: Solutions and Needs. - Todd M. Austin; Valeria Bertacco (ICCD, 2005)

Energy Optimization of Subthreshold-Voltage Sensor Network Processors. - Leyla Nazhandali; Bo Zhai; Javin Olson; Anna Reeves; Michael Minuth; Ryan Helfand; Sanjay Pant; Todd M. Austin; David T. Blaauw (ISCA, 2005)

Error Analysis for the Support of Robust Voltage Scaling. - David Roberts; Todd M. Austin; David T. Blaauw; Trevor N. Mudge; Krisztián Flautner (ISQED, 2005)

Reliability-aware data placement for partial memory protection in embedded processors. - Mojtaba Mehrara; Todd M. Austin (Memory System Performance and Correctness, 2006)

Depth-driven verification of simultaneous interfaces. - Ilya Wagner; Valeria Bertacco; Todd M. Austin (ASP-DAC, 2006)

Ultra low-cost defect protection for microprocessor pipelines. - Smitha Shyam; Kypros Constantinides; Sujay Phadke; Valeria Bertacco; Todd M. Austin (ASPLOS, 2006)

Shielding against design flaws with field repairable control logic. - Ilya Wagner; Valeria Bertacco; Todd M. Austin (DAC, 2006)

BulletProof: a defect-tolerant CMP switch architecture. - Kypros Constantinides; Stephen Plaza; Jason A. Blome; Bin Zhang 011; Valeria Bertacco; Scott A. Mahlke; Todd M. Austin; Michael Orshansky (HPCA, 2006)

Robust low power computing in the nanoscale era. - Todd M. Austin (SBCCI, 2006)

Razor: a low-power pipeline based on circuit-level timing speculation. - Todd M. Austin (SBCCI, 2006)

A self-tuning DVS processor using delay-error detection and correction. - Shidhartha Das; David Roberts; Seokwoo Lee; Sanjay Pant; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge (IEEE J. Solid State Circuits, 2006)

Low-cost protection for SER upsets and silicon defects. - Mojtaba Mehrara; Mona Attariyan; Smitha Shyam; Kypros Constantinides; Valeria Bertacco; Todd M. Austin (DATE, 2007)

Architectural implications of brick and mortar silicon manufacturing. - Martha Mercaldi Kim; Mojtaba Mehrara; Mark Oskin; Todd M. Austin (ISCA, 2007)

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. - Kypros Constantinides; Onur Mutlu; Todd M. Austin; Valeria Bertacco (MICRO, 2007)

Architecting a reliable CMP switch architecture. - Kypros Constantinides; Stephen Plaza; Jason A. Blome; Valeria Bertacco; Scott A. Mahlke; Todd M. Austin; Bin Zhang 011; Michael Orshansky (ACM Trans. Archit. Code Optim., 2007)

Microprocessor Verification via Feedback-Adjusted Markov Models. - Ilya Wagner; Valeria Bertacco; Todd M. Austin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. - Andrea Pellegrini; Kypros Constantinides; Dan Zhang 004; Shobana Sudhakar; Valeria Bertacco; Todd M. Austin (ICCD, 2008)

Polymorphic On-Chip Networks. - Martha Mercaldi Kim; John D. Davis; Mark Oskin; Todd M. Austin (ISCA, 2008)

On the rules of low-power design (and how to break them). - Todd M. Austin (ISLPED, 2008)

Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. - Kypros Constantinides; Onur Mutlu; Todd M. Austin (MICRO, 2008)

Testudo: Heavyweight security analysis via statistical sampling. - Joseph L. Greathouse; Ilya Wagner; David A. Ramos; Gautam Bhatnagar; Todd M. Austin; Valeria Bertacco; Seth Pettie (MICRO, 2008)

Reliable Systems on Unreliable Fabrics. - Todd M. Austin; Valeria Bertacco; Scott A. Mahlke; Yu Cao (IEEE Des. Test Comput., 2008)

Exploring Variability and Performance in a Sub-200-mV Processor. - Scott Hanson; Bo Zhai; Mingoo Seok; Brian Cline; Kevin Zhou; Meghna Singhal; Michael Minuth; Javin Olson; Leyla Nazhandali; Todd M. Austin; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2008)

Exploiting selective placement for low-cost memory protection. - Mojtaba Mehrara; Todd M. Austin (ACM Trans. Archit. Code Optim., 2008)

Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. - Ilya Wagner; Valeria Bertacco; Todd M. Austin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Flexible Software-Based Framework for Online Detection of Hardware Defects. - Kypros Constantinides; Onur Mutlu; Todd M. Austin; Valeria Bertacco (IEEE Trans. Computers, 2009)

Energy-Efficient Subthreshold Processor Design. - Bo Zhai; Sanjay Pant; Leyla Nazhandali; Scott Hanson; Javin Olson; Anna Reeves; Michael Minuth; Ryan Helfand; Todd M. Austin; Dennis Sylvester; David T. Blaauw (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Using introspective software-based testing for post-silicon debug and repair. - Kypros Constantinides; Todd M. Austin (DAC, 2010)

What input-language is the best choice for high level synthesis (HLS)? - Daniel Gajski; Todd M. Austin; Steve Svoboda (DAC, 2010)

Fault-based attack of RSA authentication. - Andrea Pellegrini; Valeria Bertacco; Todd M. Austin (DATE, 2010)

Highly scalable distributed dataflow analysis. - Joseph L. Greathouse; Chelsea LeBlanc; Todd M. Austin; Valeria Bertacco (CGO, 2011)

EFFEX: an embedded processor for computer vision based feature extraction. - Jason Clemons; Andrew Jones; Robert Perricone; Silvio Savarese; Todd M. Austin (DAC, 2011)

MEVBench: A mobile computer vision benchmarking suite. - Jason Clemons; Haishan Zhu; Silvio Savarese; Todd M. Austin (IISWC, 2011)

Demand-driven software race detection using hardware performance counters. - Joseph L. Greathouse; Zhiqiang Ma; Matthew I. Frank; Ramesh Peri; Todd M. Austin (ISCA, 2011)

The potential of sampling for dynamic analysis. - Joseph L. Greathouse; Todd M. Austin (PLAS, 2011)

A case for unlimited watchpoints. - Joseph L. Greathouse; Hongyi Xin; Yixin Luo; Todd M. Austin (ASPLOS, 2012)

CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. - Andrea Pellegrini; Robert Smolinski; Lei Chen; Xin Fu; Siva Kumar Sastry Hari; Junhao Jiang; Sarita V. Adve; Todd M. Austin; Valeria Bertacco (DATE, 2012)

MVSS: Michigan Visual Sonification System. - Jason Clemons; Sid Ying-Ze Bao; Silvio Savarese; Todd M. Austin; Vinay Sharma (ESPA, 2012)

EVA: An efficient vision architecture for mobile systems. - Jason Clemons; Andrea Pellegrini; Silvio Savarese; Todd M. Austin (CASES, 2013)

Schnauzer: scalable profiling for likely security bug sites. - William Arthur; Biruk Mammo; Ricardo Rodríguez Jorge; Todd M. Austin; Valeria Bertacco (CGO, 2013)

Getting in control of your control flow with control-data isolation. - William Arthur; Ben Mehne; Reetuparna Das; Todd M. Austin (CGO, 2015)

Keynote talk I: Ending the Tyranny of Amdahl's Law. - Todd M. Austin (ICCD, 2015)

Locking down insecure indirection with hardware-based control-data isolation. - William Arthur; Sahil Madeka; Reetuparna Das; Todd M. Austin (MICRO, 2015)

Bridging the Moore's Law Performance Gap with Innovation Scaling. - Todd M. Austin (ICPE, 2015)

ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. - Zelalem Birhanu Aweke; Salessawi Ferede Yitbarek; Rui Qiao 002; Reetuparna Das; Matthew Hicks; Yossi Oren; Todd M. Austin (ASPLOS, 2016)

Exploring specialized near-memory processing for data intensive operations. - Salessawi Ferede Yitbarek; Tao Yang; Reetuparna Das; Todd M. Austin (DATE, 2016)

A2: Analog Malicious Hardware. - Kaiyuan Yang 001; Matthew Hicks; Qing Dong 001; Todd M. Austin; Dennis Sylvester (IEEE Symposium on Security and Privacy, 2016)

On Architectural Support for Systems Security. - Mohit Tiwari; Todd M. Austin (IEEE Micro, 2016)

Energy efficient object detection on the mobile GP-GPU. - Fitsum Assamnew Andargie; Jonathan Rose; Todd M. Austin; Valeria Bertacco (AFRICON, 2017)

When good protections go bad: Exploiting anti-DoS measures to accelerate rowhammer attacks. - Misiker Tadesse Aga; Zelalem Birhanu Aweke; Todd M. Austin (HOST, 2017)

Øzone: Efficient execution with zero timing leakage for modern microarchitectures. - Zelalem Birhanu Aweke; Todd M. Austin (HOST, 2017)

Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. - Salessawi Ferede Yitbarek; Misiker Tadesse Aga; Reetuparna Das; Todd M. Austin (HPCA, 2017)

Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves. - Ofir Weisse; Valeria Bertacco; Todd M. Austin (ISCA, 2017)

Keynote: Peering into the post Moore's Law world. - Todd M. Austin (ISLPED, 2017)

SNIFFER: A high-accuracy malware detector for enterprise-based systems. - Evan Chavis; Harrison Davis; Yijun Hou; Matthew Hicks; Salessawi Ferede Yitbarek; Todd M. Austin; Valeria Bertacco (IVSW, 2017)

Exploiting the analog properties of digital circuits for malicious hardware. - Kaiyuan Yang 001; Matthew Hicks; Qing Dong 001; Todd M. Austin; Dennis Sylvester (Commun. ACM, 2017)

Reducing the overhead of authenticated memory encryption using delta encoding and ECC memory. - Salessawi Ferede Yitbarek; Todd M. Austin (DAC, 2018)

uSFI: Ultra-lightweight software fault isolation for IoT-class devices. - Zelalem Birhanu Aweke; Todd M. Austin (DATE, 2018)

Vulnerability-tolerant secure architectures. - Todd M. Austin; Valeria Bertacco; Baris Kasikci; Sharad Malik; Mohit Tiwari (ICCAD, 2018)

SWAN: mitigating hardware trojans with design ambiguity. - Timothy Linscott; Pete Ehrett; Valeria Bertacco; Todd M. Austin (ICCAD, 2018)

Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. - Mark Gallagher 003; Lauren Biernacki; Shibo Chen 001; Zelalem Birhanu Aweke; Salessawi Ferede Yitbarek; Misiker Tadesse Aga; Austin Harris 001; Zhixing Xu; Baris Kasikci; Valeria Bertacco; Sharad Malik; Mohit Tiwari; et al. (ASPLOS, 2019)

Smokestack: Thwarting DOP Attacks with Runtime Stack Layout Randomization. - Misiker Tadesse Aga; Todd M. Austin (CGO, 2019)

SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design. - Pete Ehrett; Todd M. Austin; Valeria Bertacco (DATE, 2019)

Wrangling in the Power of Code Pointers with ProxyCFI. - Misiker Tadesse Aga; Colton Holoday; Todd M. Austin (DBSec, 2019)

Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference. - Austin Harris 001; Shijia Wei; Prateek Sahu; Pranav Kumar; Todd M. Austin; Mohit Tiwari (MICRO, 2019)

Neverland: Lightweight Hardware Extensions for Enforcing Operating System Integrity. - Salessawi Ferede Yitbarek; Todd M. Austin (CoRR, 2019)

Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces. - Lauren Biernacki; Mark Gallagher 003; Valeria Bertacco; Todd M. Austin (HOST, 2020)

Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. - Austin Harris 001; Tarunesh Verma; Shijia Wei; Lauren Biernacki; Alex Kisil; Misiker Tadesse Aga; Valeria Bertacco; Baris Kasikci; Mohit Tiwari; Todd M. Austin (HOST, 2021)

Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. - Todd M. Austin; Austin Harris 001; Tarunesh Verma; Shijia Wei; Alex Kisil; Misiker Tadesse Aga; Valeria Bertacco; Baris Kasikci; Mohit Tiwari (HCS, 2021)

Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design. - Nishil Talati; Kyle May; Armand Behroozi; Yichen Yang 005; Kuba Kaszyk; Christos Vasiladiotis; Tarunesh Verma; Lu Li; Brandon Nguyen; Jiawen Sun; John Magnus Morton; Agreen Ahmadi; et al. (HPCA, 2021)

Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets. - Pete Ehrett; Todd M. Austin; Valeria Bertacco (ICCD, 2021)

A Defense-Inspired Benchmark Suite. - Pete Ehrett; Nathan Block; Bing Schaefer; Adrian Berding; John Paul Koenig; Pranav Srinivasan; Valeria Bertacco; Todd M. Austin (ISPASS, 2021)

ChipAdvisor: A Machine Learning Approach for Mapping Applications to Heterogeneous Systems. - Hiwot Tadese Kassa; Tarunesh Verma; Todd M. Austin; Valeria Bertacco (ISQED, 2021)

VIP-Bench: A Benchmark Suite for Evaluating Privacy-Enhanced Computation Frameworks. - Lauren Biernacki; Meron Zerihun Demissie; Kidus Birkayehu Workneh; Galane Basha Namomsa; Plato Gebremedhin; Fitsum Assamnew Andargie; Brandon Reagen; Todd M. Austin (SEED, 2021)

Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses. - Lauren Biernacki; Mark Gallagher 003; Zhixing Xu; Misiker Tadesse Aga; Austin Harris 001; Shijia Wei; Mohit Tiwari; Baris Kasikci; Sharad Malik; Todd M. Austin (ACM J. Emerg. Technol. Comput. Syst., 2021)

PriMax: maximizing DSL application performance with selective primitive acceleration. - Nicholas Wendt; Todd M. Austin; Valeria Bertacco (DAC, 2022)

Twine: A Chisel Extension for Component-Level Heterogeneous Design. - Shibo Chen 001; Yonathan Fisseha; Jean-Baptiste Jeannin; Todd M. Austin (DATE, 2022)

Sequestered Encryption: A Hardware Technique for Comprehensive Data Privacy. - Lauren Biernacki; Meron Zerihun Demissie; Kidus Birkayehu Workneh; Fitsum Assamnew Andargie; Todd M. Austin (SEED, 2022)

These Aren't The Caches You're Looking For: Stochastic Channels on Randomized Caches. - Tarunesh Verma; Achilleas Anastasopoulos; Todd M. Austin (SEED, 2022)

Security Verification of Low-Trust Architectures. - Qinhan Tan; Yonathan Fisseha; Shibo Chen 001; Lauren Biernacki; Jean-Baptiste Jeannin; Sharad Malik; Todd M. Austin (CCS, 2023)

Exploring the Efficiency of Data-Oblivious Programs. - Lauren Biernacki; Biniyam Mengist Tiruye; Meron Zerihun Demissie; Fitsum Assamnew Andargie; Brandon Reagen; Todd M. Austin (ISPASS, 2023)

Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions. - Venkat Nitin Patnala; Sai Manoj Pudukotai Dinakarrao; Guru Venkataramani; Jie Chen 020; Preet Derasari; Milos Doroslovacki; Fan Yao; Hongyu Fang; Meron Demissie; Todd M. Austin; Lauren Biernacki; Saket Upadhyay; et al. (CASES, 2024)

Octal: Efficient Automatic Data-Oblivious Program Transformations to Eliminate Side-Channel Leakage. - Biniyam Mengist Tiruye; Lauren Biernacki; Tersiteab Adem; Petros Mola; Todd M. Austin (SecDev, 2024)

Channelizer: Explainable ML Inference for Validating Side-Channel Resistant Systems. - Donayam Benti; Todd M. Austin (SEED, 2024)

Zipper: Latency-Tolerant Optimizations for High-Performance Buses. - Shibo Chen 001; Hailun Zhang; Todd M. Austin (ASP-DAC, 2025)

DOME: Automated Validation of Data-Oblivious Program Execution. - Donayam Benti; Todd M. Austin (HOST, 2025)