A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme. - Shinji Komori; Hidehiro Takata; Todhixuki Tamura; Fumixsdu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Hiroaki Nishikawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)