Hierarchical top-down layout design method for VLSI chip. - Tohru Adachi; Hitoshi Kitazawa; Mitsuyoshi Nagatani; Tsuneta Sudo (DAC, 1982)

An Integrated Design Automation System for VLSI Circuits. - Osamu Karatsu; Tamio Hoshino; Makoto Endo; Hitoshi Kitazawa; Tohru Adachi; Kazuhiro Ueda (IEEE Des. Test, 1985)

An automatic cell pattern generation system for CMOS transistor-pair array LSI. - Hiroshi Miyashita; Tohru Adachi; Kazuhiro Ueda (Integr., 1986)

Top-Down Layout for Hierarchical Custom Design. - Kazuhiro Ueda; Hitoshi Kitazawa; Tohru Adachi; Ikuo Harada (IEEE Des. Test, 1987)

Software Environment for 500 MHz VLSI Test System "ULTIMATE". - Tohru Adachi; M. Tanno; Tsuneta Sudo (ITC, 1988)

MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. - Ken Namura; Johannes Maximilian Kühn; Tohru Adachi; H. Imachi; H. Kaneko; T. Kato; Go Watanabe; Naoto Tanaka; S. Kashihara; Hiroshi Miyashita; Y. Tomonaga; Ryosuke Okuta; et al. (VLSI Circuits, 2021)