On the big Mu in the affine scaling algorithm. - Tohru Ishihara; Masakazu Kojima (Math. Program., 1993)

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. - Tohru Ishihara; Hiroto Yasuura (ISLPED, 1996)

Power-Pro: Programmable Power Management Architecture. - Tohru Ishihara; Hiroto Yasuura (ASP-DAC, 1998)

Instruction Scheduling for Power Reduction in Processor-Based System Design. - Hiroyuki Tomiyama; Tohru Ishihara; Akihiko Inoue; Hiroto Yasuura (DATE, 1998)

Voltage scheduling problem for dynamically variable voltage processors. - Tohru Ishihara; Hiroto Yasuura (ISLPED, 1998)

Way-predicting set-associative cache for high performance and low energy consumption. - Koji Inoue; Tohru Ishihara; Kazuaki J. Murakami (ISLPED, 1999)

Real-Time Task Scheduling for a Variable Voltage Processor. - Takanori Okuma; Tohru Ishihara; Hiroto Yasuura (ISSS, 1999)

A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. - Tohru Ishihara; Hiroto Yasuura (DATE, 2000)

Flexible System LSI for Embedded Systems and Its Optimization Techniques. - Akihiko Inoue; Tohru Ishihara; Hiroto Yasuura (Des. Autom. Embed. Syst., 2000)

A system level memory power optimization technique using multiple supply and threshold voltages. - Tohru Ishihara; Kunihiro Asada (ASP-DAC, 2001)

Software Energy Reduction Techniques for Variable-Voltage Processors. - Takanori Okuma; Hiroto Yasuura; Tohru Ishihara (IEEE Des. Test Comput., 2001)

An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. - Tohru Ishihara; Kunihiro Asada (ASP-DAC/VLSI Design, 2002)

A Power Minimization Technique for Arithmetic Circuits by Cell Selection. - Masanori Muroyama; Tohru Ishihara; Akihiko Hyodo; Hiroto Yasuura (ASP-DAC/VLSI Design, 2002)

Comparative Study On Verilog-Based And C-Based Hardware Design Education. - Tohru Ishihara; Satoshi Komatsu; Makoto Ikeda; Masahiro Fujita; Kunihiro Asada (MSE, 2003)

A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. - Tohru Ishihara; Farzan Fallah (DATE, 2005)

A cache-defect-aware code placement algorithm for improving the performance of processors. - Tohru Ishihara; Farzan Fallah (ICCAD, 2005)

Energy-Efficient Embedded System Design at 90nm and Below - A System-Level Perspective -. - Tohru Ishihara (ISHPC, 2005)

A non-uniform cache architecture for low power system design. - Tohru Ishihara; Farzan Fallah (ISLPED, 2005)

An Energy Characterization Framework for Software-Based Embedded Systems. - Donghoon Lee; Tohru Ishihara; Masanori Muroyama; Hiroto Yasuura; Farzan Fallah (ESTIMedia, 2006)

A Simulation-Based Soft Error Estimation Methodology for Computer Systems. - Makoto Sugihara; Tohru Ishihara; Masanori Muroyama; Koji Hashimoto (ISQED, 2006)

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. - Maziar Goudarzi; Tohru Ishihara; Hiroto Yasuura (ASP-DAC, 2007)

Task scheduling for reliable cache architectures of multiprocessor systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (DATE, 2007)

Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. - Yuriko Ishitobi; Tohru Ishihara; Hiroto Yasuura (ESTIMedia, 2007)

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. - Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada; Tohru Ishihara (EUC (1), 2008)

Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. - Maziar Goudarzi; Tohru Ishihara (ACM Great Lakes Symposium on VLSI, 2008)

Simultaneous optimization of memory configuration and code allocation for low power embedded systems. - Tadayuki Matsumura; Tohru Ishihara; Hiroto Yasuura (ACM Great Lakes Symposium on VLSI, 2008)

Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. - Maziar Goudarzi; Tohru Ishihara; Hamid Noori (HiPEAC, 2008)

Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. - Maziar Goudarzi; Tohru Ishihara (ISLPED, 2008)

Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. - Maziar Goudarzi; Tadayuki Matsumura; Tohru Ishihara (ISVLSI, 2008)

Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. - Masanori Muroyama; Tohru Ishihara; Hiroto Yasuura (PATMOS, 2008)

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. - Tohru Ishihara; Seiichiro Yamaguchi; Yuriko Ishitobi; Tadayuki Matsumura; Yuji Kunitake; Yuichiro Oyama; Yusuke Kaneda; Masanori Muroyama; Toshinori Sato (SASP, 2008)

Value-dependence of SRAM leakage in deca-nanometer technologies. - Maziar Goudarzi; Tohru Ishihara (IEICE Electron. Express, 2008)

Way-Scaling to Reduce Power of Cache with Delay Variation. - Maziar Goudarzi; Tadayuki Matsumura; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (IEICE Trans. Electron., 2008)

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation. - Maziar Goudarzi; Tohru Ishihara; Hiroto Yasuura (Microelectron. J., 2008)

Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories. - Lovic Gauthier; Tohru Ishihara (ESTIMedia, 2009)

An Optimization Technique for Low-Energy Embedded Memory Systems. - Tadayuki Matsumura; Tohru Ishihara; Hiroto Yasuura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. - Seiichiro Yamaguchi; Yuriko Ishitobi; Tohru Ishihara; Hiroto Yasuura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. - Lovic Gauthier; Tohru Ishihara; Hideki Takase; Hiroyuki Tomiyama; Hiroaki Takada (CASES, 2010)

An RTOS in hardware for energy efficient software-based TCP/IP processing. - Naotaka Maruyama; Tohru Ishihara; Hiroto Yasuura (SASP, 2010)

A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems. - Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation. - Maziar Goudarzi; Tohru Ishihara (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. - Yuriko Ishitobi; Tohru Ishihara; Hiroto Yasuura (J. Signal Process. Syst., 2010)

Developing an integrated verification and debug methodology. - Akitoshi Matsuda; Tohru Ishihara (DATE, 2011)

An integrated optimization framework for reducing the energy consumption of embedded real-time applications. - Hideki Takase; Gang Zeng; Lovic Gauthier; Hirotaka Kawashima; Noritoshi Atsumi; Tomohiro Tatematsu; Yoshitake Kobayashi; Shunitsu Kohara; Takenori Koshiro; Tohru Ishihara; Hiroyuki Tomiyama; Hiroaki Takada (ISLPED, 2011)

Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. - Takumi Okuhira; Tohru Ishihara (PATMOS, 2011)

Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications. - Lovic Gauthier; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. - Maziar Goudarzi; Tohru Ishihara; Hamid Noori (Trans. High Perform. Embed. Archit. Compil., 2011)

Loop instruction caching for energy-efficient embedded multitasking processors. - Ji Gu; Tohru Ishihara; Kyungsoo Lee (ESTIMedia, 2012)

I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays. - Kyungsoo Lee; Tohru Ishihara (ESTIMedia, 2012)

A flexible structure of standard cell and its optimization method for near-threshold voltage operation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (ICCD, 2012)

A Standard Cell Optimization Method for Near-Threshold Voltage Operations. - Masahiro Kondo; Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2012)

A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems. - Ji Gu; Tohru Ishihara (SMARTGREENS, 2012)

A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems. - Kyungsoo Lee; Tohru Ishihara (SMARTGREENS, 2012)

Processor Energy Characterization for Compiler-Assisted Software Energy Reduction. - Lovic Gauthier; Tohru Ishihara (J. Electr. Comput. Eng., 2012)

Analysis and comparison of XOR cell structures for low voltage circuit design. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2013)

DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems. - Kyungsoo Lee; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

DLIC: Decoded loop instructions caching for energy-aware embedded processors. - Ji Gu; Hui Guo 001; Tohru Ishihara (ACM Trans. Embed. Comput. Syst., 2013)

Variation-aware Flip-Flop energy optimization for ultra low voltage operation. - Tatsuya Kamakari; Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2014)

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2014)

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications. - Hideki Takase; Gang Zeng; Lovic Gauthier; Hirotaka Kawashima; Noritoshi Atsumi; Tomohiro Tatematsu; Yoshitake Kobayashi; Takenori Koshiro; Tohru Ishihara; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Microarchitectural-level statistical timing models for near-threshold circuit design. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ASP-DAC, 2015)

Energy reduction by built-in body biasing with single supply voltage operation. - Norihiro Kamae; Islam A. K. M. Mahfuzul; Akira Tsuchiya; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2015)

An energy-efficient on-chip memory structure for variability-aware near-threshold operation. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2015)

An impact of process variation on supply voltage dependence of logic path delay variation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (VLSI-DAT, 2015)

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. - Islam A. K. M. Mahfuzul; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEEE J. Solid State Circuits, 2015)

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. - Tatsuya Kamakari; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ASP-DAC, 2016)

An integrated optical parallel adder as a first step towards light speed data processing. - Tohru Ishihara; Akihiko Shinya; Koji Inoue; Kengo Nozaki; Masaya Notomi (ISOCC, 2016)

Variability- and correlation-aware logical effort for near-threshold circuit design. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2016)

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2016)

Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. - Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2016)

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. - Tatsuya Kamakari; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. - Tadashi Kishimoto; Tohru Ishihara; Hidetoshi Onodera (VLSI-DAT, 2017)

A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. - Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. - Takumi Egawa; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Shota Kita; Kengo Nozaki; Kenta Takata; Masaya Notomi (ICRC, 2018)

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2018)

Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. - Yosuke Okamura; Tohru Ishihara; Hidetoshi Onodera (IOLTS, 2018)

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. - Hongjie Xu; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2018)

Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. - Tatsuhiro Higuchi; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2018)

An Integrated Nanophotonic Parallel Adder. - Tohru Ishihara; Akihiko Shinya; Koji Inoue; Kengo Nozaki; Masaya Notomi (ACM J. Emerg. Technol. Comput. Syst., 2018)

Minimum Energy Point Tracking with All-Digital On-Chip Sensors. - Jun Shiomi; Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (J. Low Power Electron., 2018)

BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ASP-DAC, 2019)

An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. - Tohru Ishihara; Jun Shiomi; Naoki Hattori; Yutaka Masuda; Akihiko Shinya; Masaya Notomi (PHOTONICS@SC, 2019)

A Design Method of a Cell-Based Amplifier for Body Bias Generation. - Takuya Koyanagi; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Electron., 2019)

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. - Hongjie Xu; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (Integr., 2019)

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2020)

Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. - Khyati Kiyawat; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (ISVLSI, 2020)

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ISVLSI, 2020)

Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. - Yutaka Masuda; Jun Nagayama; TaiYu Cheng; Tohru Ishihara; Yoichi Momiyama; Masanori Hashimoto (DATE, 2021)

Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. - Kazuki Yoshisue; Yutaka Masuda; Tohru Ishihara (IOLTS, 2021)

Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. - Takumi Komori; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (ISQED, 2021)

Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. - Naoki Hattori; Jun Shiomi; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. - Lingxiao Hou; Yutaka Masuda; Tohru Ishihara (ASP-DAC, 2022)

Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. - Naoki Hattori; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (DAC, 2022)

Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. - Taisei Ichikawa; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (ISVLSI, 2022)

Energy efficient OEO conversion and its applications to photonic integrated systems. - Akihiko Shinya; Kengo Nozaki; Shota Kita; Tohru Ishihara; Shinji Matsuo; Masaya Notomi (OFC, 2022)

DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. - Takumi Komori; Yutaka Masuda; Tohru Ishihara (RTCSA, 2022)

Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. - Jun Shiomi; Shogo Terada; Tohru Ishihara; Hidetoshi Onodera (SOCC, 2022)

Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. - Takumi Komori; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. - Yutaka Masuda; Jun Nagayama; TaiYu Cheng; Tohru Ishihara; Yoichi Momiyama; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. - Jiaxuan Lu; Yutaka Masuda; Tohru Ishihara (DATE, 2023)

Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. - Yusei Honda; Yutaka Masuda; Tohru Ishihara (IOLTS, 2023)

A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. - Tai-Feng Chen; Yutaka Masuda; Tohru Ishihara (SOCC, 2023)

An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. - Lingxiao Hou; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. - Yutaka Masuda; Yusei Honda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. - Jiaxuan Lu; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. - Takumi Komori; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Panel Discussions: "Sustainable AI: Emerging Architectures, Devices, and Quantum Computing Towards Future Computing". - Tohru Ishihara; Jangwoo Kim; Kazutoshi Kobayashi; Jose Martinez (COOL CHIPS, 2025)

Piecewise-Linear Approximation of Self-Attention and Its Accuracy-Aware Training for Area-Efficient Vision Transformer Inference Accelerator. - Teppei Kawamura; Yutaka Masuda; Tohru Ishihara (ISQED, 2025)

Optoelectronic Pipeline Architecture of Convolutional RNN for Energy Efficient Inference at the Speed of Light. - Chunlu Wang; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Electron., 2025)

Message from the Editor-in-Chief. - Tohru Ishihara (IPSJ Trans. Syst. LSI Des. Methodol., 2025)