25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. - Tohru Kaneko; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. - Tohru Kaneko; Yuya Kimura; Koji Hirose; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2016)

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. - Tohru Kaneko; Yuya Kimura; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. - Zheng Sun 001; Hanli Liu; Dexian Tang; Hongye Huang; Tohru Kaneko; Rui Wu 001; Wei Deng 001; Kenichi Okada 001 (ESSCIRC, 2018)

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Wei Deng 001; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits. - Tohru Kaneko; Koji Hirose; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. - Tohru Kaneko; Yuya Kimura; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Zhijie Chen; Wei Deng 001; Rui Wu 001; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (IEEE J. Solid State Circuits, 2019)

A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. - Zheng Sun 001; Hanli Liu; Hongye Huang; Dexian Tang; Dingxin Xu; Tohru Kaneko; Zheng Li 021; Jian Pang; Rui Wu 001; Wei Deng 001; Atsushi Shirane; Kenichi Okada 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)