An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. - Tohru Furuyama; Takashi Ohsawa; Yousei Nagahama; Hiroto Tanaka; Yohji Watanabe; Tohru Kimura; Kazuyoshi Muraoka; Kenji Natori (IEEE J. Solid State Circuits, 1989)

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs. - Tohru Furuyama; Hidemi Ishiuchi; Hiroyasu Tanaka; Yoshihisa Watanabe; Yusuke Kohyama; Tohru Kimura; Kazuyoshi Muraoka; Souichi Sugiura; Kenji Natori (IEEE J. Solid State Circuits, 1990)

A 300-MHz 16-b BiCMOS video signal processor. - Toshiaki Inoue; Junichi Goto; Masakazu Yamashina; Kazumasa Suzuki; Masahiro Nomura; Youichi Koseki; Tohru Kimura; Takao Atsumo; Masato Motomura; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; et al. (IEEE J. Solid State Circuits, 1993)

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. - Kazuyuki Nakamura; Shigeru Kuhara; Tohru Kimura; Masahide Takada; Hisamitsu Suzuki; Hiroshi Yoshida; Tohru Yamazaki (IEEE J. Solid State Circuits, 1994)

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. - Nobuyuki Yamashita; Tohru Kimura; Yoshihiro Fujita; Yoshiharu Aimoto; Takashi Manabe; Shin'ichiro Okazaki; Kazuyuki Nakamura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1994)

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. - Tohru Kimura; Kazuyuki Nakamura; Yoshiharu Aimoto; Takashi Manabe; Nobuyuki Yamashita; Yoshihiro Fujita; Shin'ichiro Okazaki; Masakazu Yamashina (IEEE J. Solid State Circuits, 1995)

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. - Hiraki Koike; Tetsuya Otsuki; Tohru Kimura; Masao Fukuma; Yoshihiro Hayashi; Yukihiko Maejima; Kazushi Amanuma; Nobuhira Tanabe; Takeo Matsuki; Shinobu Saito; Tsuneo Takeuchi; Souta Kobayashi; et al. (IEEE J. Solid State Circuits, 1996)

A 3.84 gips integrated memory array processor. - Yoshihiro Fujita; Nobuyuki Yamashita; Tohru Kimura; Kazuyuki Nakamura; Shin'ichiro Okazaki (Syst. Comput. Jpn., 1996)

A Wireless Dual-Link System for Sensor Network Applications. - Tohru Kimura; Hitoshi Yano; Yuuichi Aoki; Nobuhide Yoshida; Jun Noda; Teruki Sukenari; Yusuke Konishi; Toshiyasu Nakao; Akitake Mitsuhashi; Daigo Taguchi (ISSCC, 2008)