A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. - Marcel A. Kossel; Christian Menolfi; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Peter Buchmann; Lukas Kull; Toke Meyer Andersen; Thomas Morf (ISSCC, 2013)

An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. - Marcel A. Kossel; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Christian Menolfi; Peter Buchmann; Lukas Kull; Toke Meyer Andersen; Thomas Morf (ISSCC, 2013)

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. - Lukas Kull; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (ISSCC, 2013)

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. - Marcel A. Kossel; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Christian Menolfi; Peter Buchmann; Lukas Kull; Toke Meyer Andersen; Thomas Morf (IEEE J. Solid State Circuits, 2013)

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. - Lukas Kull; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (IEEE J. Solid State Circuits, 2013)

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. - Lukas Kull; Jan Plíva; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (A-SSCC, 2014)

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. - Pier Andrea Francese; Thomas Toifl; Matthias Braendli; Peter Buchmann; Thomas Morf; Marcel A. Kossel; Christian Menolfi; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel (ESSCIRC, 2014)

A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. - Marcel A. Kossel; Christian Menolfi; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Thomas Morf; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel (ESSCIRC, 2014)

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. - Toke Meyer Andersen; Florian Krismer; Johann W. Kolar; Thomas Toifl; Christian Menolfi; Lukas Kull; Thomas Morf; Marcel A. Kossel; Matthias Braendli; Peter Buchmann; Pier Andrea Francese (ISSCC, 2014)

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. - Lukas Kull; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (ISSCC, 2014)

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. - Pier Andrea Francese; Thomas Toifl; Peter Buchmann; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Toke Meyer Andersen (IEEE J. Solid State Circuits, 2014)

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. - Hazar Yueksel; Lukas Kull; Andreas Burg 001; Matthias Braendli; Peter Buchmann; Pier Andrea Francese; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Danny Luu; Thomas Toifl (ESSCIRC, 2015)

20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. - Toke Meyer Andersen; Florian Krismer; Johann Walter Kolar; Thomas Toifl; Christian Menolfi; Lukas Kull; Thomas Morf; Marcel A. Kossel; Matthias Braendli; Pier Andrea Francese (ISSCC, 2015)

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. - Pier Andrea Francese; Thomas Toifl; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel; Alessandro Cevrero; Danny Luu (ISSCC, 2015)

Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. - Lukas Kull; Jan Plíva; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (IEEE J. Solid State Circuits, 2016)