Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). - Takayuki Kawahara; Masashi Horiguchi; Yoshiki Kawajiri; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

256-Mb DRAM circuit technologies for file applications. - Goro Kitsukawa; Masashi Horiguchi; Yoshiki Kawajiri; Takayuki Kawahara; Takesada Akiba; Yasushi Kawase; Toshikazu Tachibana; Takeshi Sakai; Masakazu Aoki; Syoji Shukuri; Kazuhiko Sagara; Ryo Nagai; et al. (IEEE J. Solid State Circuits, 1993)

A charge recycle refresh for Gb-scale DRAM's in file applications. - Takayulu Kawahara; Yoshiki Kawajiri; Masashi Horiguchi; Takesada Akiba; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. - Hiroyuki Mizuno; Nozomu Matsuzaki; Kenichi Osada; Toshinobu Shinbo; Nagatoshi Ohki; Hiroshi Ishida; Koichiro Ishibashi; Tokuo Kure (IEEE J. Solid State Circuits, 1996)

Single-electron memory for giga-to-tera bit storage. - Kazuo Yano; Tomoyuki Ishii; Toshiaki Sano; Toshiyuki Mine; Fumio Murai; Takashi Hashimoto; Takashi Kobayashi 002; Tokuo Kure; Koichi Seki (Proc. IEEE, 1999)