A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. - Koji Nii; Hideshi Maeno; Tokuya Osawa; Shuhei Iwade; Shinpei Kayano; Hiroshi Shibata (IEEE J. Solid State Circuits, 1995)

A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (ISSCC, 2007)

A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (IEICE Trans. Electron., 2009)