Tolerating data access latency with register preloading. - William Y. Chen; Scott A. Mahlke; Wen-mei W. Hwu; Tokuzo Kiyohara; Pohua P. Chang (ICS, 1992)

Using Profile Information to Assist Advaced Compiler Optimization and Scheduling. - William Y. Chen; Roger A. Bringmann; Scott A. Mahlke; Sadun Anik; Tokuzo Kiyohara; Nancy J. Warter; Daniel M. Lavery; Wen-mei W. Hwu; Richard E. Hank; John C. Gyllenhaal (LCPC, 1992)

Code scheduling for VLIW/superscalar processors with limited register files. - Tokuzo Kiyohara; John C. Gyllenhaal (MICRO, 1992)

Register Connection: A New Approach to Adding Registers into Instruction Set Architectures. - Tokuzo Kiyohara; Scott A. Mahlke; William Y. Chen; Roger A. Bringmann; Richard E. Hank; Sadun Anik; Wen-mei W. Hwu (ISCA, 1993)

The superblock: An effective technique for VLIW and superscalar compilation. - Wen-mei W. Hwu; Scott A. Mahlke; William Y. Chen; Pohua P. Chang; Nancy J. Warter; Roger A. Bringmann; Roland G. Ouellette; Richard E. Hank; Tokuzo Kiyohara; Grant E. Haab; John G. Holm; Daniel M. Lavery (J. Supercomput., 1993)

Multi-Threaded Processor for Image Generation. - Takayuki Sagishima; Kozo Kimura; Hiroaki Hirata; Tokuzo Kiyohara; Shigeo Asahara; Takao Onoye; Isao Shirakawa (ISCAS, 1994)

An architectural extension to the media core processor for HDTV applications. - Kosuke Yoshioka; Hiroyuki Oka; Hideshi Nishida; Ryuji Matsuura; Tokuzo Kiyohara (APCCAS (1), 2002)