Context-sensitive static transistor-level IR analysis. - Weiqing Guo; Yu Zhong; Tom Burd (ICCAD, 2008)

Constraint Management and Checking in Template-Based Circuit Designs. - Richard Bartolotti; Tom Burd; Brian McMinn; Arun Chandra (MTV, 2009)

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. - Aaron Grenat; Sriram Sundaram; Stephen Kosonocky; Ravinder Rachala; Sriram Sambamurthy; Steven Liepe; Miguel Rodriguez; Tom Burd; Adam Clark; Michael Austin; Samuel Naffziger (ISSCC, 2016)

Carrizo: A High Performance, Energy Efficient 28 nm APU. - Benjamin Munger; David Akeson; Srikanth Arekapudi; Tom Burd; Harry R. Fair III; Jim Farrell; Dave Johnson 002; Guhan Krishnan; Hugh McIntyre; Edward McLellan; Samuel Naffziger; Russell Schreiber; et al. (IEEE J. Solid State Circuits, 2016)

Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. - Sriram Sundaram; Aaron Grenat; Samuel Naffziger; Tom Burd; Stephen Kosonocky; Steven Liepe; Ravinder Rachala; Miguel Rodriguez; Michael Austin; Sriram Sambamurthy (IEEE J. Solid State Circuits, 2017)

Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads. - Prachi Shukla; Derrick Aguren; Tom Burd; Ayse K. Coskun; John Kalamatianos (DATE, 2023)

"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. - Benjamin Munger; Kathy Wilcox; Jeshuah Sniderman; Chuck Tung; Brett Johnson; Russell Schreiber; Carson Henrion; Kevin Gillespie; Tom Burd; Harry R. Fair III; Dave Johnson 002; Jonathan White; et al. (ISSCC, 2023)