A Fast 1024-Point FFT Architecture. - Tom Chen 001; Li Zhu (ICPP (1), 1991)

An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. - Tom Chen 001; Glen Sunada (ICCD, 1992)

A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. - Tom Chen 001; Glen Sunada (ITC, 1992)

Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. - Tom Chen 001; Glen Sunada (IEEE Trans. Very Large Scale Integr. Syst., 1993)

An expandable column fft architecture using circuit switching networks. - Tom Chen 001; Li Zhu (J. VLSI Signal Process., 1993)

On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. - Fahad M. Alzahrani; Tom Chen 001 (ICCD, 1994)

COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. - Glen Sunada; Jain Jin; Matt Berzins; Tom Chen 001 (ICCD, 1994)

Defects, Fault Coverage, Yield and Cost in Board Manufacturing. - Mick Tegethoff; Tom Chen 001 (ITC, 1994)

Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. - Mick Tegethoff; Tom Chen 001 (ITC, 1994)

Performance and Area Optimization of VLSI Systems Using Genetic Algorithms. - Xiao-Dong Wang; Tom Chen 001 (VLSI Design, 1995)

ASIC Yield Estimation at Early Design Cycle. - Von-Kyoung Kim; Mick Tegethoff; Tom Chen 001 (ITC, 1996)

Assessing Neural Networks as Guides for Testing Activities. - Charles Anderson 001; Anneliese von Mayrhauser; Tom Chen 001 (IEEE METRICS, 1996)

Sensitivity Analysis of Critical Parameters in Board Test. - Mick Tegethoff; Tom Chen 001 (IEEE Des. Test Comput., 1996)

A real-time high performance edge detector for computer vision applications. - Fahad M. Alzahrani; Tom Chen 001 (ASP-DAC, 1997)

ASIC Manufacturing Test Cost Prediction at Early Design Stage. - Von-Kyoung Kim; Tom Chen 001; Mick Tegethoff (ITC, 1997)

Simulation Techniques for the Manufacturing Test of MCMs. - Mick Tegethoff; Tom Chen 001 (J. Electron. Test., 1997)

A Real-Time Edge Detector: Algorithm and VLSI Architecture. - Fahad M. Alzahrani; Tom Chen 001 (Real Time Imaging, 1997)

Fast Antirandom (FAR) Test Generation. - Anneliese von Mayrhauser; Andre Bai; Tom Chen 001; Charles Anderson 001; Amjad Hajjar (HASE, 1998)

Assessing Defect Coverage of Memory Testing Algorithms. - Von-Kyoung Kim; Tom Chen 001 (Great Lakes Symposium on VLSI, 1999)

Fault Coverage Estimation for Early Stage of VLSI Design. - Von-Kyoung Kim; Tom Chen 001; Mick Tegethoff (Great Lakes Symposium on VLSI, 1999)

How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. - Tom Chen 001; Anneliese von Mayrhauser; Amjad Hajjar; Charles Anderson 001; Mehmet Sahinoglu (HASE, 1999)

Efficient Verification of Behavioral Models Using Sequential Sampling Technique. - Tom Chen 001; Isabelle Munn; Anneliese von Mayrhauser; Amjad Hajjar (VLSI, 1999)

Assessing merged DRAM/Logic technology. - Ytong-Bin Kim; Tom W. Chen (Integr., 1999)

VLSI Architecture for Real-Time Edge Linking. - Amjad Hajjar; Tom Chen 001 (IEEE Trans. Pattern Anal. Mach. Intell., 1999)

On comparing functional fault coverage and defect coverage for memory testing. - Von-Kyoung Kim; Tom Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

COBRA: a 100-MOPS single-chip programmable and expandable FFT. - Tom Chen 001; Glen Sunada; Jain Jin (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. - Jinsang Kim; Tom Chen 001 (CAMP, 2000)

Measuring routing congestion for multi-layer global routing. - Tom W. Chen; Alkan Cengiz (ACM Great Lakes Symposium on VLSI, 2000)

On statistical behavior of branch coverage in testing behavioral VHDL models. - Amjad Hajjar; Tom Chen 001; Anneliese von Mayrhauser (HLDVT, 2000)

On choosing test criteria for behavioral level hardware design verification. - Anneliese von Mayrhauser; Tom Chen 001; Jan Kok; Chuck Anderson 001; Anita Read; Amjad Hajjar (HLDVT, 2000)

Segmentation of Image Sequences Using SOFM Networks. - Jinsang Kim; Tom Chen 001 (ICPR, 2000)

Achieving the Quality of Verification for Behavioral Models with Minimum Effort. - Tom Chen 001; Anneliese von Mayrhauser; Amjad Hajjar; Charles Anderson 001; Mehmet Sahinoglu (ISQED, 2000)

On the impact of on-chip inductance on signal nets under the influence of power grid noise. - Tom Chen 001 (DATE, 2001)

High quality behavioral verification using statistical stopping criteria. - Amjad Hajjar; Tom Chen 001; Isabelle Munn; Anneliese Amschler Andrews; Maria Bjorkman (DATE, 2001)

Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. - Tom Chen 001 (ISQED, 2001)

Stopping Criteria Comparison: Towards High Quality Behavioral Verification. - Amjad Hajjar; Tom Chen 001; Isabelle Munn; Anneliese Amschler Andrews; Maria Bjorkman (ISQED, 2001)

Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. - Jinsang Kim; Tom Chen 001 (VIIP, 2001)

Multiple feature clustering for image sequence segmentation. - Jinsang Kim; Tom Chen 001 (Pattern Recognit. Lett., 2001)

On Mixed PTL/Static Logic for Low-power and High-speed Circuits. - Geun Rae Cho; Tom Chen 001 (VLSI Design, 2001)

An Accurate Coverage Forecasting Model for Behavioral Model Verification. - Amjad Hajjar; Tom Chen 001 (DELTA, 2002)

On The Impact of Technology Scaling On Mixed PTL/Static Circuits. - Geun Rae Cho; Tom Chen 001 (ICCD, 2002)

Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. - Geun Rae Cho; Tom Chen 001 (ISQED, 2002)

Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. - Amjad Hajjar; Tom Chen 001 (ISQED, 2002)

On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. - Geun Rae Cho; Tom Chen 001 (IWLS, 2002)

Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. - Geun Rae Cho; Tom Chen 001 (SEAL, 2002)

Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. - Tom Chen 001; Andre Bai; Amjad Hajjar; Anneliese Amschler Andrews; Charles Anderson 001 (J. Electron. Test., 2002)

Design of a CMOS test chip for package models and I/O characteristics verification. - Chetan Despande; Tom Chen 001 (ASP-DAC, 2003)

Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. - Tom Chen 001; Amjad Hajjar (ISQED, 2003)

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. - Geun Rae Cho; Tom Chen 001 (ISQED, 2003)

A Rule-Based Software Testing Method for VHDL Models. - Anneliese Amschler Andrews; Andrew O'Fallon; Tom Chen 001 (VLSI-SOC, 2003)

On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. - Geun Rae Cho; Tom Chen 001 (VLSI Design, 2003)

A VLSI architecture for video-object segmentation. - Jinsang Kim; Tom Chen 001 (IEEE Trans. Circuits Syst. Video Technol., 2003)

A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations. - Tom W. Chen; Justin Gregg (DATE, 2004)

Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. - Gerald Esch Jr.; Tom Chen 001 (DELTA, 2004)

RUBASTEM: A Method for Testing VHDL Behavioral Models. - Anneliese Amschler Andrews; Andrew O'Fallon; Tom Chen 001 (HASE, 2004)

Post Silicon Power/Performance Optimization in the Presence of ProcessVariations Using Individual Well Adaptive Body Biasing (IWABB). - Justin Gregg; Tom W. Chen (ISQED, 2004)

Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. - Tom Chen 001; Amjad Hajjar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. - Geun Rae Cho; Tom Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. - Gerald Esch Jr.; Tom Chen 001 (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Stability analysis of active clock deskewing systems using a control theoretic approach. - Vinil Varghese; Tom Chen 001; Peter Michael Young (ASP-DAC, 2005)

Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. - Ajith Chandy; Tom Chen 001 (DATE, 2005)

Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. - Vinil Varghese; Tom Chen 001; Peter Michael Young (DATE, 2005)

Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm. - Justin Gregg; Tom W. Chen (ISQED, 2005)

PEER: Enriching Secondary Engineering Education Through a College Summer Camp. - Justin Gregg; Tom W. Chen (MSE, 2005)

International Symposium on Quality Electronic Design. - Daniela De Venuto; Tom Chen 001 (Microelectron. J., 2005)

A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. - Medha Kulkarni; Tom Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Modeling multiple input switching of CMOS gates in DSM technology using HDMR. - Jayashree Sridharan; Tom Chen 001 (DATE, 2006)

Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations. - Vaibhav Nawale; Thomas W. Chen (ICCAD, 2006)

Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization. - Alkan Cengiz; Tom W. Chen (ISVLSI, 2006)

A Progressive Two-Stage Global Routing for Macro-Cell Based Designs. - Alkan Cengiz; Tom W. Chen (VLSI Design, 2006)

Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. - Jayashree Sridharan; Tom Chen 001 (VLSI Design, 2006)

Steady state noise modeling in computer chips using neural networks. - Vaibhav Nawale; Thomas W. Chen (Artificial Intelligence and Applications, 2007)

Power andPerformance Analysis for Early Design Space Exploration. - Charles Thangaraj; Tom Chen 001 (ISVLSI, 2007)

Editorial. - Daniela De Venuto; Tom Chen 001 (Microelectron. J., 2007)

Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. - Justin Gregg; Tom W. Chen (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. - Charles Thangaraj; Tom Chen 001 (DELTA, 2008)

Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking. - Tsau-Shuan Wu; Alkan Cengiz; Tom W. Chen (DSD, 2008)

Design target exploration for meeting time-to-market using pareto analysis. - Charles Thangaraj; Tom Chen 001 (ISCAS, 2008)

On power and performance tradeoff of L2 cache compression. - Chandrika Jena; Tim Mason; Tom Chen 001 (APCCAS, 2010)

On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. - Allen Chen; Ryan Hoppal; Tom Chen 001 (DSD, 2010)

Fast Evaluation of Analog Circuits Using Linear Programming. - Zach Cashero; Allen Chen; Ryan Hoppal; Tom Chen 001 (ISVLSI, 2010)

Rapid design space exploration using legacy design data and technology scaling trend. - Charles Thangaraj; Alkan Cengiz; Tom Chen 001 (Integr., 2010)

Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. - Charles Thangaraj; Robert Pownall; Phil Nikkel; Guangwei Yuan; Kevin L. Lear; Tom Chen 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A 0.18µm CMOS 2nd Order Sigma-Delta Modulator for Low-power Biosensor Applications. - Ryan Selby; Tom Chen 001 (BIODEVICES, 2013)

A 2nd Order CMOS Sigma-Delta Modulator Design Suitable for Low-Power Biosensor Applications. - Ryan Selby; Tom Chen 001 (BIOSTEC (Selected Papers), 2013)

A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications. - Kristin Scholfield; Tom Chen 001 (DSD, 2013)

A 0.18µm CMOS switched-capacitor amplifier using current-starving inverter based op-amp for low-power biosensor applications. - Ryan Selby; Kern Tucker; William Wilson; Tom Chen 001 (LASCAS, 2013)

A current-starved inverter-based differential amplifier design for ultra-low power applications. - William Wilson; Tom Chen 001; Ryan Selby (LASCAS, 2013)

Design of a 50MΩ Transimpedance Amplifier with 0.98fa/vHz Input Inferred Noise in a 0.18µM CMOS Technology. - William Wilson; Tom Chen 001 (BIODEVICES, 2014)

A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C. - Hai Chi; Tom Chen 001 (ISVLSI, 2014)

A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical Applications. - Lang Yang; Thomas W. Chen (DSD, 2015)

A low power frequency synthesizer for biosensor applications in the MedRadio band. - Abhiram Reddy Gundla; Tom Chen 001 (MWSCAS, 2015)

Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design. - Mozammel Hossain; Chirag Desai; Tom Chen 001; Vikas Agarwal (Integr., 2015)

Design of an integrated microelectrode array system for high spatiotemporal resolution chemical imaging. - William Tedjo; Rachel Feeny; Chad Eitel; Luke Schwerdtfeger; Stacy Willett; Charles Henry; Stuart Tobet; Tom Chen 001 (BioCAS, 2016)

A compact signal generation and acquisition circuit for electrochemical impedance spectroscopy. - Lang Yang; Tom Chen 001 (BioCAS, 2016)

A 0.2 nJ/bit QPSK transmitter with tuning for process variation for biomedical telemetry in the MedRadio band of 401-457 MHz. - Abhiram Reddy Gundla; Tom Chen 001 (MWSCAS, 2016)

An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz. - Abhiram Reddy Gundla; Tom Chen 001 (VLSI-SoC, 2016)

A novel high-throughput method for table look-up based analog design automation. - Yishai Statter; Tom Chen 001 (Integr., 2016)

Γ (Gamma): A SaaS-enabled fast and accurate analog design System. - Yishai Statter; Tom Chen 001 (Integr., 2016)

A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis. - Mozammel Hossain; John Badar; Jack DiLullo; Tom Chen 001 (Microprocess. Microsystems, 2016)

A handheld electrochemical sensing platform for point-of-care diagnostic applications. - Lang Yang; Tom Chen 001 (BioCAS, 2017)

A Holistic Approach to Transforming Undergraduate Electrical Engineering Education. - Anthony A. Maciejewski; Thomas W. Chen; Zinta S. Byrne; Michael A. De Miranda; Laura B. Sample Mcmeeking; Branislav M. Notaros; Ali Pezeshki; Sourajeet Roy; Andrea M. Leland; Melissa D. Reese; Alma H. Rosales; Thomas J. Siller; et al. (IEEE Access, 2017)

Study of Real-Time Spatial and Temporal Behavior of Bacterial Biofilms Using 2-D Impedance Spectroscopy. - Caleb Begly; David Ackart; Julian Mylius; Randall Basaraba; Adam J. Chicco; Thomas W. Chen (IEEE Trans. Biomed. Circuits Syst., 2020)

An Integrated Biosensor System With a High-Density Microelectrode Array for Real-Time Electrochemical Imaging. - William Tedjo; Thomas W. Chen (IEEE Trans. Biomed. Circuits Syst., 2020)