A Monolithic Asynchronous Sample-Rate Converter for Digital Audio. - Robert Adams 001; Tom Kwan (ISCAS, 1993)

A stereo asynchronous digital sample-rate converter for digital audio. - Robert Adams 001; Tom Kwan (IEEE J. Solid State Circuits, 1994)

A stereo multibit ΣΔ DAC with asynchronous master-clock interface. - Tom Kwan; Robert Adams 001; Robert Libert (IEEE J. Solid State Circuits, 1996)

A single-chip universal cable set-top box/modem transceiver. - Lionel J. D'Luna; Loke Tan; Dean W. Mueller; Joe L. Laskowski; Kelly B. Cameron; Jind-Yeh Lee; David Gee; Jason S. Monroe; Honman S. Law; Jason Chang; Myles H. Wakayama; Tom Kwan; et al. (IEEE J. Solid State Circuits, 1999)

A single-chip universal digital satellite receiver with 480-MHz IF input. - Alan Y. Kwentus; Patrick Pai; Steven Jaffe; Ray Gomez; Shauhyuarn Sean Tsai; Tom Kwan; Hing T. Hung; Young J. Shin; Vin Hue; Darwin Cheung; Raheel A. Khan; Christopher M. Ward; et al. (IEEE J. Solid State Circuits, 1999)

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit. - Ali Afsahi; Jacob J. Rael; Arya Behzad; Hung-Ming Chien; Michael Pan; Stephen Au; Adedayo Ojo; C. Paul Lee; Seema Butala Anand; Kevin Chien; Stephen Wu 003; Rozi Roufoogaran; et al. (IEEE J. Solid State Circuits, 2008)

A 70 dB MTPR Integrated Programmable Gain/Bandwidth Fourth-Order Chebyshev High-Pass Filter for ADSL/VDSL Receivers in 65 nm CMOS. - Fang Lin; Xinyu Yu; Sumant Ranganathan; Tom Kwan (IEEE J. Solid State Circuits, 2009)

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS. - Michael A. Inerfield; Abhishek Kamath; Feng Su; Jason Hu; Xinyu Yu; Victor Fong; Omar Alnaggar; Fang Lin; Tom Kwan (VLSIC, 2014)

A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS. - Harsh Mehta; Gautham Krishnamurthy; Michael A. Inerfield; Fang Lin; Tom Kwan (VLSIC, 2014)

A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer. - Guowen Wei; Pradeep Shettigar; Feng Su; Xinyu Yu; Tom Kwan (VLSIC, 2015)