Multipurpose DRAM architecture for optimal power, performance, and product flexibility. - Wayne F. Ellis; John E. Barth Jr.; Sri Divakaruni; Jeffrey H. Dreibelbis; Anatol Furman; Erik L. Hedberg; Hsing-San Lee; Thomas M. Maffitt; Christopher P. Miller; Charles H. Stapper; Howard L. Kalter (IBM J. Res. Dev., 1995)

A 16-Mb MRAM featuring bootstrapped write drivers. - Dietmar Gogl; Christian Arndt; John C. Barwin; Alexander Bette; John K. DeBrosse; Earl T. Gow; Heinz Hoenigschmid; Stefan Lammers; Mark C. Lamorey; Yu Lu; Tom Maffitt; Kim Maloney; et al. (IEEE J. Solid State Circuits, 2005)

Design considerations for MRAM. - Thomas M. Maffitt; John K. DeBrosse; John A. Gabric; Earl T. Gow; Mark C. Lamorey; John S. Parenteau; Dennis R. Willmott; Mark A. Wood; William J. Gallagher (IBM J. Res. Dev., 2006)

A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell. - Gael F. Close; Urs Frey; Jack Morrish; Richard Jordan; Scott C. Lewis; Tom Maffitt; M. J. BrightSky; Christoph Hagleitner; Chung Hon Lam; Evangelos Eleftheriou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing. - John K. DeBrosse; Thomas M. Maffitt; Yutaka Nakamura; Guenole Jan; Po-Kang Wang (CICC, 2015)

12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. - Igor Arsovski; Michael Fragano; Robert M. Houle; Akhilesh Patil; Van Butler; Raymond Kim; Ramon Rodriguez; Tom Maffitt; Joseph J. Oler; John Goss; Christopher Parkinson; Michael A. Ziegerhofer; et al. (ISSCC, 2017)