Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey. - W. Deweerd; Vidya Kaushik; J. Chen; Y. Shimamoto; Tom Schram; L.-Å. Ragnarsson; Annelies Delabie; Luigi Pantisano; B. Eyckens; J. W. Maes (Microelectron. Reliab., 2005)

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors. - Tom Schram; L.-Å. Ragnarsson; G. S. Lujan; W. Deweerd; J. Chen; W. Tsai; K. Henson; R. J. P. Lander; J. C. Hooker; J. Vertommen (Microelectron. Reliab., 2005)

Mechanism of O2-anneal induced Vfb shifts of Ru gated stacks. - Z. Li; Tom Schram; Luigi Pantisano; A. Stesmans; Thierry Conard; S. Shamuilia; V. V. Afanasiev; A. Akheyar; Sven Van Elshocht; D. P. Brunco; W. Deweerd; Y. Naoki; et al. (Microelectron. Reliab., 2007)

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

Impact of Off State Stress on advanced high-K metal gate NMOSFETs. - Alessio Spessot; Marc Aoulaiche; Moonju Cho; Jacopo Franco; Tom Schram; Romain Ritzenthaler; Ben Kaczer (ESSDERC, 2014)

Off-state stress degradation mechanism on advanced p-MOSFETs. - Moonju Cho; Alessio Spessot; Ben Kaczer; Marc Aoulaiche; Romain Ritzenthaler; Tom Schram; Pierre Fazan; Naoto Horiguchi; Dimitri Linten (ICICDT, 2015)

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. - Romain Ritzenthaler; Tom Schram; M. J. Cho; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Christian Caillat; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Assessment of SiGe quantum well transistors for DRAM peripheral applications. - Romain Ritzenthaler; Tom Schram; Geert Eneman; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs. - Alessio Spessot; Romain Ritzenthaler; Tom Schram; Marc Aoulaiche; Moonju Cho; Maria Toledano-Luque; Naoto Horiguchi; Pierre Fazan (ICICDT, 2015)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

WS2 transistors on 300 mm wafers with BEOL compatibility. - Tom Schram; Quentin Smets; Benjamin Groven; M. H. Heyne; E. Kunnen; A. Thiam; Katia Devriendt; Annelies Delabie; Dennis Lin; M. Lux; Daniele Chiappe; I. Asselberghs; et al. (ESSDERC, 2017)

Analysis of BTI in 300 mm integrated dual-gate WS2 FETs. - L. Panarella; Quentin Smets; Devin Verreck; Tom Schram; Daire Cott; I. Asselberghs; Ben Kaczer (DRC, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs. - L. Panarella; Ben Kaczer; Quentin Smets; Devin Verreck; Tom Schram; Daire Cott; Dennis Lin; Stanislav Tyaginov; I. Asselberghs; Cesar J. Lockhart de la Rosa; Gouri Sankar Kar; Valeri Afanas'ev (IRPS, 2023)

Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer. - Souvik Ghosh 001; Quentin Smets; S. Banerjee; Tom Schram; Koen Kennes; R. Verheyen; P. Kumar; M.-E. Boulon; Benjamin Groven; H. M. Silva; Shreya Kundu; Daire Cott; et al. (VLSI Technology and Circuits, 2023)

Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach. - Shreya Kundu; D. H. van Doip; Tom Schram; Quentin Smets; S. Banerjee; Benjamin Groven; Daire Cott; Stefan Decoster; P. Bezard; F. Lazzarino; K. Banerjee; Souvik Ghosh 001; et al. (VLSI Technology and Circuits, 2023)

EOT Scaling Via 300mm MX2 Dry Transfer - Steps Toward a Manufacturable Process Development and Device Integration. - S. Ghosh; A. Kruv; Quentin Smets; Tom Schram; D. J. Leech; T. Ding; V. Turkani; Benjamin Groven; A. Dangel; G. Probst; Thomas Uhrmann; Markus Wimplinger; et al. (VLSI Technology and Circuits, 2024)