A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100. - Tom Shimizu; Toyohiko Yoshida; Yuichi Saito; Masahito Matsuo; Tatsuya Enomoto (COMPCON, 1988)

A 1.71-million transistor CMOS CPU chip with a testable cache architecture. - Yuichi Saito; Yukihiko Shimazu; Tom Shimizu; Kenji Shirai; Isao Fujioka; Yoshitetsu Nishiwaki; Junichi Hinata; Yoshiki Shimotsuma; Masayoshi Sakao (IEEE J. Solid State Circuits, 1993)

The E-CELL project: towards integrative simulation of cellular processes. - Masaru Tomita; Kenta Hashimoto; Koichi Takahashi; Yuri Matsuzaki; Ryo Matsushima; Katsuyuki Yugi; Fumihiko Miyoshi; Hisako Nakano; Yusuke Saito; Tom Shimizu; Yoichi Nakayama (RECOMB, 2000)