Low Power Coarse-Grained Reconfigurable Instruction Set Processor. - Francisco Barat; Murali Jayapala; Tom Vander Aa; Rudy Lauwereins; Geert Deconinck; Henk Corporaal (FPL, 2003)

Instruction buffering exploration for low energy VLIWs with instruction clusters. - Tom Vander Aa; Murali Jayapala; Francisco Barat; Geert Deconinck; Rudy Lauwereins; Francky Catthoor; Henk Corporaal (ASP-DAC, 2004)

L0 Cluster Synthesis and Operation Shuffling. - Murali Jayapala; Tom Vander Aa; Francisco Barat; Francky Catthoor; Henk Corporaal; Geert Deconinck (PATMOS, 2004)

Design Style Case Study for Embedded Multi Media Compute Nodes. - Andy Lambrechts; Tom Vander Aa; Murali Jayapala; Guillermo Talavera; Anthony Leroy; Adelina Shickova; Francisco Barat; Bingfeng Mei; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; et al. (RTSS, 2004)

L0 buffer energy optimization through scheduling and exploration. - Murali Jayapala; Tom Vander Aa; Francisco Barat; Geert Deconinck; Francky Catthoor; Henk Corporaal (SAC, 2004)

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. - Andy Lambrechts; Praveen Raghavan; Anthony Leroy; Guillermo Talavera; Tom Vander Aa; Murali Jayapala; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; Frédéric Robert; Jordi Carrabina (ASAP, 2005)

Combining Data and Instruction Memory Energy Optimizations for Embedded Applications. - Tom Vander Aa; Francky Catthoor; Henk Corporaal; Geert Deconinck (ESTIMedia, 2005)

Instruction buffering exploration for low energy embedded processors. - Tom Vander Aa; Murali Jayapala; Francisco Barat; Geert Deconinck; Rudy Lauwereins; Henk Corporaal; Francky Catthoor (J. Embed. Comput., 2005)

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. - Murali Jayapala; Francisco Barat; Tom Vander Aa; Francky Catthoor; Henk Corporaal; Geert Deconinck (IEEE Trans. Computers, 2005)

Hardware and a Tool Chain for ADRES. - Bjorn De Sutter; Bingfeng Mei; T. Andrei Bartic; Tom Vander Aa; Mladen Berekovic; Jean-Yves Mignolet; Kris Croes; Paul Coene; Miro Cupac; Aïssa Couvreur; Andy Folens; Steven Dupont; et al. (ARC, 2006)

Instruction Transfer And Storage Exploration for Low Energy VLIWs. - Tom Vander Aa; Murali Jayapala; Henk Corporaal; Francky Catthoor; Geert Deconinck (SiPS, 2006)

A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. - Tom Vander Aa; Bingfeng Mei; Bjorn De Sutter (CASES, 2007)

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. - Matthias Hartmann; Vasileios (Vassilis) Pantazis; Tom Vander Aa; Mladen Berekovic; Christian Hochberger; Bjorn De Sutter (ESTIMedia, 2007)

Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. - Andres Garcia; Mladen Berekovic; Tom Vander Aa (ASAP, 2008)

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays. - Bjorn De Sutter; Paul Coene; Tom Vander Aa; Bingfeng Mei (LCTES, 2008)

Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. - Mladen Berekovic; Frank Bouwens; Tom Vander Aa; Diederik Verkest (PATMOS, 2008)

Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. - Bingfeng Mei; Bjorn De Sutter; Tom Vander Aa; M. Wouters; Andreas Kanstein; Steven Dupont (J. Signal Process. Syst., 2008)

Compilation techniques for CGRAs: exploring all parallelization approaches. - Tom Vander Aa; Praveen Raghavan; Scott A. Mahlke; Bjorn De Sutter; Aviral Shrivastava; Frank Hannig (CODES+ISSS, 2010)

Architectures for cognitive radio testbeds and demonstrators - An overview. - Oscar Gustafsson; Kiarash Amiri; Dennis Andersson; Anton Blad; Christian Bonnet; Joseph R. Cavallaro; Jeroen Declerck; Antoine Dejonghe; Patrik Eliardsson; Miguel Glassee; Aawatif Hayar; Lieven Hollevoet; et al. (CrownCom, 2010)

SDR platform for 802.11n and 3-GPP LTE. - Jeroen Declerck; Praveen Raghavan; Frederik Naessens; Tom Vander Aa; Lieven Hollevoet; Antoine Dejonghe; Liesbet Van der Perre (ICSAMOS, 2010)

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. - Matthias Hartmann; Vasileios (Vassilis) Pantazis; Tom Vander Aa; Mladen Berekovic; Christian Hochberger (J. Signal Process. Syst., 2010)

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors. - Bjorn De Sutter; Osman Allam; Praveen Raghavan; Roeland Vandebriel; Hans Cappelle; Tom Vander Aa; Bingfeng Mei (J. Signal Process. Syst., 2010)

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor. - Hideki Yamada; Toshiyuki Yamagishi; Tomoya Suzuki; Kuniaki Ito; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (COOL Chips, 2011)

A multi-threaded coarse-grained array processor for wireless baseband. - Tom Vander Aa; Martin Palkovic; Matthias Hartmann; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (SASP, 2011)

High level analysis of trade-offs across different partitioning schemes for wireless applications. - Prashant Agrawal; Robert Fasthuber; Praveen Raghavan; Tom Vander Aa; Ubaid Ahmad; Liesbet Van der Perre; Francky Catthoor (SiPS, 2011)

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors. - Tomoya Suzuki; Hideki Yamada; Toshiyuki Yamagishi; Daisuke Takeda; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (IEEE Micro, 2011)

Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and exploration. - Tom Vander Aa; Panagiotis Theocharis (CODES+ISSS, 2012)

Power Estimation at Different Abstraction Levels for Wireless Baseband Processors. - Martin Palkovic; Peter Debacker; Prabhat Avasare; Steven Dupont; Tom Vander Aa (J. Low Power Electron., 2012)

Data memory optimization in LTE downlink. - Namita Sharma 001; Tom Vander Aa; Prashant Agrawal; Praveen Raghavan; Preeti Ranjan Panda; Francky Catthoor (ICASSP, 2013)

Hard versus Soft Software Defined Radio. - Wim Meeus; Tom Vander Aa; Praveen Raghavan; Dirk Stroobandt (VLSID, 2014)

ExaShark: a scalable hybrid array kit for exascale simulation. - Imen Chakroun; Tom Vander Aa; Bruno De Fraine; Tom Haber; Roel Wuyts; Wolfgang De Meuter (SpringSim (HPS), 2015)

Array Interleaving - An Energy-Efficient Data Layout Transformation. - Namita Sharma 001; Preeti Ranjan Panda; Francky Catthoor; Praveen Raghavan; Tom Vander Aa (ACM Trans. Design Autom. Electr. Syst., 2015)

Exploring a Distributed Iterative Reconstructor Based on Split Bregman Using PETSc. - Estefania Serrano; Tom Vander Aa; Roel Wuyts; Francisco Javier García Blas; Jesús Carretero 001; Mónica Abella (ICA3PP Workshops, 2016)

Exploring Parallel Implementations of the Bayesian Probabilistic Matrix Factorization. - Imen Chakroun; Tom Haber; Tom Vander Aa; Thomas Kovac (PDP, 2016)

Distributed Bayesian Probabilistic Matrix Factorization. - Tom Vander Aa; Imen Chakroun; Tom Haber (ICCS, 2017)

Distributed Matrix Factorization using Asynchrounous Communication. - Tom Vander Aa; Imen Chakroun; Tom Haber (CoRR, 2017)

Cache-efficient Gradient Descent Algorithm. - Imen Chakroun; Tom Vander Aa; Thomas J. Ashby (ESANN, 2018)

HyperLoom: A Platform for Defining and Executing Scientific Pipelines in Distributed Environments. - Vojtech Cima; Stanislav Böhm; Jan Martinovic; Jiri Dvorský; Katerina Janurová; Tom Vander Aa; Thomas J. Ashby; Vladimir I. Chupakhin (PARMA-DITAM@HiPEAC, 2018)

Enhancing Machine Learning Optimization Algorithms by Leveraging Memory Caching (Research Poster). - Imen Chakroun; Tom Vander Aa; Tom Ashby (HPCS, 2018)

A high-level library for multidimensional arrays programming in computational science. - Imen Chakroun; Tom Vander Aa; Bruno De Fraine; Tom Haber; Pascal Costanza; Roel Wuyts (Concurr. Comput. Pract. Exp., 2018)

SMURFF: a High-Performance Framework for Matrix Factorization. - Tom Vander Aa; Imen Chakroun; Thomas J. Ashby (AICAS, 2019)

Virtual Screening on FPGA. - Tom Vander Aa; Tom Ashby; Roel Wuyts (BNAIC/BENELEARN, 2019)

SMURFF: A High-Performance Framework for Matrix Factorization Methods. - Tom Vander Aa; Imen Chakroun; Tom Ashby; Jaak Simm; Adam Arany; Yves Moreau; Thanh Le Van; José Felipe Golib Dzib; Jörg K. Wegner; Vladimir I. Chupakhin; Hugo Ceulemans; Roel Wuyts; et al. (BNAIC/BENELEARN, 2019)

Reviewing Data Access Patterns and Computational Redundancy for Machine Learning Algorithms. - Imen Chakroun; Tom Vander Aa; Tom Ashby (CoRR, 2019)

Guidelines for enhancing data locality in selected machine learning algorithms. - Imen Chakroun; Tom Vander Aa; Tom Ashby (Intell. Data Anal., 2019)

A High-Performance Implementation of Bayesian Matrix Factorization with Limited Communication. - Tom Vander Aa; Xiangju Qin; Paul Blomstedt; Roel Wuyts; Wilfried Verachtert; Samuel Kaski (ICCS (6), 2020)

Industry-scale application and evaluation of deep learning for drug target prediction. - Noé Sturm; Andreas Mayr; Thanh Le Van; Vladimir I. Chupakhin; Hugo Ceulemans; Jörg K. Wegner; José Felipe Golib Dzib; Nina Jeliazkova; Yves Vandriessche; Stanislav Böhm; Vojtech Cima; Jan Martinovic; et al. (J. Cheminformatics, 2020)

Distributing intelligence for object detection using edge computing. - Imen Chakroun; Tom Vander Aa; Roel Wuyts; Wilfried Verachtert (CLOUD, 2021)

Privacy-Preserving Multi-Party Machine Learning for Object Detection. - Imen Chakroun; Tom Vander Aa; Roel Wuyts; Wilfried Verarcht (GCAIoT, 2021)

Virtual Screening on FPGA: Performance and Energy versus Effort. - Tom Vander Aa; Tom Haber; Thomas J. Ashby; Roel Wuyts; Wilfried Verachtert (CoRR, 2022)