A P1500 Compliant Programable BistShell for Embedded Memories. - Sandeep Koranne; Tom Waayers; Robert Beurze; Clemens Wouters; Sunil Kumar; G. S. Visweswara (MTDT, 2001)

EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. - Bart Vermeulen; Tom Waayers; Sjaak Bakker (ITC, 2002)

Core-Based Scan Architecture for Silicon Debug. - Bart Vermeulen; Tom Waayers; Sandeep Kumar Goel (ITC, 2002)

Enhanced Reduced Pin-Count Test for Full-Scan Design. - Harald P. E. Vranken; Tom Waayers; Hérvé Fleury; David Lelouvier (J. Electron. Test., 2002)

An extension to JTAG for at-speed debug on a system. - Leon van de Logt; Frank van der Heyden; Tom Waayers (ITC, 2003)

An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. - Tom Waayers (ITC, 2003)

Multi-TAP Controller Architecture for Digital System Chips. - Bart Vermeulen; Tom Waayers; Sjaak Bakker (J. Electron. Test., 2003)

Infrastructure for modular SOC testing. - Erik Jan Marinissen; Tom Waayers (CICC, 2004)

Extending the Digital Core-based Test Methodology to Support Mixed-Signal. - Geert Seuren; Tom Waayers (ITC, 2004)

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. - Tom Waayers; Erik Jan Marinissen; Maurice Lousberg (Asian Test Symposium, 2005)

Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain. - Tom Waayers; Richard Morren; Roberto Grandi (ITC, 2005)

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. - Tom Waayers; Richard Morren; Xijiang Lin; Mark Kassab (ITC, 2010)

Industrial Application of IEEE P1687 for an Automotive Product. - Martin Keim; Tom Waayers; Richard Morren; Friedrich Hapke; Rene Krenz-Baath (DSD, 2013)