FSM Based Functional Test Generation Framework for VHDL. - Vacius Jusas; Tomas Neverdauskas (ICIST, 2012)

Novel Method to Generate Tests for VHDL. - Vacius Jusas; Tomas Neverdauskas (ICIST, 2013)

Combining Software and Hardware Test Generation Methods to Verify VHDL Models. - Vacius Jusas; Tomas Neverdauskas (Inf. Technol. Control., 2013)

Stimuli generator for testing processes in VHDL. - Vacius Jusas; Tomas Neverdauskas (NORCHIP, 2014)

Stimuli generation framework for testing multiple processes in VHDL. - Vacius Jusas; Tomas Neverdauskas (Inf. Technol. Control., 2014)