Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. - Tomas Pecenka; Zdenek Kotásek; Lukás Sekanina; Josef Strnadel (Evolvable Hardware, 2005)

NetFlow Probe Intended for High-Speed Networks. - Martin Zádník; Tomas Pecenka; Jan Korenek (FPL, 2005)

FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. - Tomas Pecenka; Zdenek Kotásek; Lukás Sekanina (DDECS, 2006)

Testability Estimation Based on Controllability and Observability Parameters. - Tomas Pecenka; Josef Strnadel; Zdenek Kotásek; Lukás Sekanina (DSD, 2006)

Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. - Josef Strnadel; Tomas Pecenka; Zdenek Kotásek (Comput. Informatics, 2008)

Evolution of synthetic RTL benchmark circuits with predefined testability. - Tomas Pecenka; Lukás Sekanina; Zdenek Kotásek (ACM Trans. Design Autom. Electr. Syst., 2008)