CMOS Standard Cells Characterization for IDDQ Testing. - Witold A. Pleskacz; Tomasz Borejko; Wieslaw Kuzmicz (DFT, 2002)

DefSim: CMOS Defects on Chip for Research and Education. - Witold A. Pleskacz; Tomasz Borejko; Andrzej Walkanis; Viera Stopjaková; Artur Jutman; Raimund Ubar (LATW, 2006)

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. - Marcin J. Beresinski; Tomasz Borejko; Witold A. Pleskacz; Viera Stopjaková (DDECS, 2008)

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. - Tomasz Borejko; Witold A. Pleskacz (DDECS, 2008)

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. - Witold A. Pleskacz; Viera Stopjaková; Tomasz Borejko; Artur Jutman; Andrzej Walkanis (IEEE Trans. Ind. Electron., 2008)

Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. - Jacek Gradzki; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2009)

A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. - Jacek Gradzki; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2010)

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. - Michal Lukaszewicz; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2011)

PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. - Krzysztof Siwiec; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2011)

CAD tool for PLL Design. - Krzysztof Siwiec; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2011)

LC-VCO design automation tool for nanometer CMOS technology. - Krzysztof Siwiec; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2012)

IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology. - Mariusz Derlecki; Tomasz Borejko; Witold A. Pleskacz (MIXDES, 2015)

Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications. - Aleh Halauko; Tomasz Borejko; Witold A. Pleskacz (MIXDES, 2015)

A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring. - Krzysztof Siwiec; Krzysztof Marcinek; Tomasz Borejko; Adam Jarosz; Jakub Kopanski; Ewa Kurjata-Pfitzner; Pawel Narczyk; Maciej Plasota; Andrzej Wielgus; Witold A. Pleskacz (MIXDES, 2015)

BioSoC: Highly integrated System-on-Chip for health monitoring. - Krzysztof Siwiec; Krzysztof Marcinek; Piotr Boguszewicz; Tomasz Borejko; Aleh Halauko; Adam Jarosz; Jakub Kopanski; Ewa Kurjata-Pfitzner; Pawel Narczyk; Maciej Plasota; Andrzej Wielgus; Witold A. Pleskacz (DDECS, 2016)

Dedicated chip for pulse oximetry measurements. - Cezary Kolacinski; Jerzy Wasowski; Andrzej Szymanski; Adam Jarosz; Ewa Kurjata-Pfitzner; Tomasz Borejko; Krzysztof Siwiec; Witold A. Pleskacz (EWDTS, 2016)

The integrated transmitter and receiver modules for pulse oximeter system. - Cezary Kolacinski; Andrzej Szymanski; Adam Jarosz; Ewa Kurjata-Pfitzner; Jerzy Wasowski; Tomasz Borejko; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2016)

Importance of on-chip inductor modeling in radio frequency integrated circuits. - Daniel Pietron; Tomasz Borejko; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2017)

DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology. - Adam Borkowski; Tomasz Borejko; Witold A. Pleskacz (MIXDES, 2019)

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. - Tomasz Borejko; Krzysztof Marcinek; Krzysztof Siwiec; Pawel Narczyk; Adam Borkowski; Igor Butryn; Arkadiusz W. Luczyk; Daniel Pietron; Maciej Plasota; Szymon Reszewicz; Lukasz Wiechowski; Witold A. Pleskacz (Sensors, 2020)

Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069. - Tomasz Borejko; Krzysztof Marcinek; Krzysztof Siwiec; Pawel Narczyk; Adam Borkowski; Igor Butryn; Arkadiusz W. Luczyk; Daniel Pietron; Maciej Plasota; Szymon Reszewicz; Lukasz Wiechowski; Witold A. Pleskacz (Sensors, 2020)