FSM State Assignment Methods for Low-Power Design. - Valery Salauyou; Tomasz Grzes (CISIM, 2007)

A Scalable Distributed Architecture for Emulating Unreliable Networks for Testing Multimedia Systems. - Marek Parfieniuk; Tomasz Lukaszuk; Tomasz Grzes (IP&C, 2013)

FPGA in Rough Set Based Core and Reduct Computation. - Tomasz Grzes; Maciej Kopczynski; Jaroslaw Stepaniuk (RSKT, 2013)

The First Step Toward Processor for Rough Set Methods. - Jaroslaw Stepaniuk; Maciej Kopczynski; Tomasz Grzes (Fundam. Informaticae, 2013)

Generating Core in Rough Set Theory: Design and Implementation on FPGA. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (RSEISP, 2014)

FPGA in Rough-Granular Computing: Reduct Generation. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (WI-IAT (1), 2014)

Minimization Method of Finite State Machines for Low Power Design. - Adam Klimowicz; Valery Solov'ev; Tomasz Grzes (DSD, 2015)

Computation of Cores in Big Datasets: An FPGA Approach. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (RSKT, 2015)

Hardware Supported Rough Sets Based Rules Generation for Big Datasets. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (CISIM, 2016)

Core for Large Datasets: Rough Sets on FPGA. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (Fundam. Informaticae, 2016)

Rough Sets Based LEM2 Rules Generation Supported by FPGA. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (Fundam. Informaticae, 2016)

Hardware Supported Rule-Based Classification on Big Datasets. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (IJCRS (1), 2017)

Multiple Codes State Assignment and Code Length Reduction for Power Minimization of Finite State Machines. - Tomasz Grzes (CISIM, 2018)

High-Speed Finite State Machine Design by State Splitting. - Damian Borecki; Valery Salauyou; Tomasz Grzes (DepCoS-RELCOMEX, 2018)

Two FPGA Devices in the Problem of Finding Minimal Reducts. - Mateusz Choromanski; Tomasz Grzes; Piotr Honko (CISIM, 2019)

Lossless and Lossy Audio Codecs for Low-Performance Microcontrollers for Use in IoT. - Tomasz Grzes (CISIM, 2019)

Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation. - Tomasz Grzes; Maciej Kopczynski (IJCRS, 2019)

The Synthesis Method of High-Speed Finite State Machines in FPGA. - Valery Salauyou; Damian Borecki; Tomasz Grzes (CISIM, 2020)

Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets. - Maciej Kopczynski; Tomasz Grzes (ICARCV, 2020)

Breadth search strategies for finding minimal reducts: towards hardware implementation. - Mateusz Choromanski; Tomasz Grzes; Piotr Honko (Neural Comput. Appl., 2020)

Development of Digital Competences of Elementary School Teachers with a Life-Long Learning Approach. - Michal Czolombitko; Tomasz Grzes; Maciej Kopczynski; Urszula Kuzelewska; Anna Lupinska-Dubicka; Dorota Mozyrska; Joanna Panasiuk (CISIM, 2021)

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets. - Maciej Kopczynski; Tomasz Grzes (J. Artif. Intell. Soft Comput. Res., 2021)

Survey on dialogue systems including slavic languages. - Krzysztof Wolk; Agnieszka Wolk; Dominika Cecylia Wnuk; Tomasz Grzes; Ida Skubis (Neurocomputing, 2022)

FPGA supported rough set reduct calculation for big datasets. - Maciej Kopczynski; Tomasz Grzes (J. Intell. Inf. Syst., 2022)

Voice Long Distance Transmission Using Audio Codec for Low-Performance Microcontrollers and LoRa Communication for Use in IoT. - Tomasz Grzes (CISIM, 2024)