A synthesis oriented omniscient manual editor. - Tomasz S. Czajkowski; Jonathan Rose (FPGA, 2004)

Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. - Tomasz S. Czajkowski; Stephen Dean Brown (DAC, 2007)

Fast toggle rate computation for FPGA circuits. - Tomasz S. Czajkowski; Stephen Dean Brown (FPL, 2008)

Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. - Tomasz S. Czajkowski; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. - Tomasz S. Czajkowski; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

LegUp: high-level synthesis for FPGA-based processor/accelerator systems. - Andrew Canis; Jongsok Choi; Mark Aldham; Victor Zhang; Ahmed Kammoona; Jason Helge Anderson; Stephen Brown 003; Tomasz S. Czajkowski (FPGA, 2011)

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. - Jongsok Choi; Kevin Nam; Andrew Canis; Jason Helge Anderson; Stephen Brown 003; Tomasz S. Czajkowski (FCCM, 2012)

Impact of FPGA architecture on resource sharing in high-level synthesis. - Stefan Hadjis; Andrew Canis; Jason Helge Anderson; Jongsok Choi; Kevin Nam; Stephen Brown 003; Tomasz S. Czajkowski (FPGA, 2012)

From opencl to high-performance hardware on FPGAS. - Tomasz S. Czajkowski; Utku Aydonat; Dmitry Denisenko; John Freeman; Michael Kinsner; David Neto; Jason Wong; Peter Yiannacouras; Deshanand P. Singh (FPL, 2012)

From software to accelerators with LegUp high-level synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Ruolong Lian; Qijing Huang 001; Nazanin Calagar; Marcel Gort; Jia Jun Qin; Mark Aldham; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (CASES, 2013)

Harnessing the power of FPGAs using altera's OpenCL compiler. - Deshanand P. Singh; Tomasz S. Czajkowski; Andrew C. Ling (FPGA, 2013)

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. - Andrew Canis; Jongsok Choi; Mark Aldham; Victor Zhang; Ahmed Kammoona; Tomasz S. Czajkowski; Stephen Dean Brown; Jason Helge Anderson (ACM Trans. Embed. Comput. Syst., 2013)

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. - Blair Fort; Andrew Canis; Jongsok Choi; Nazanin Calagar; Ruolong Lian; Stefan Hadjis; Yu Ting Chen; Mathew Hall; Bain Syrowik; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (EUC, 2014)

Silicon Verification using High-Level Design Tools (Abstract Only). - Tomasz S. Czajkowski (FPGA, 2015)

High-Level Design Tools for Floating Point FPGAs. - Deshanand P. Singh; Bogdan Pasca 001; Tomasz S. Czajkowski (FPGA, 2015)

High-level synthesis of software-customizable floating-point cores. - Samridhi Bansal; Hsuan Hsiao; Tomasz S. Czajkowski; Jason Helge Anderson (DATE, 2018)

Modeling and Rendering of Volumetric Clouds in Real-Time with Unreal Engine 4. - Lukasz Nowak; Artur Bak; Tomasz S. Czajkowski; Konrad Wojciechowski (ICCVG, 2018)

Real-Time Simulation of Animated Characters Crowd in Unreal Engine 4. - Michal Rosenbeiger; Artur Bak; Tomasz S. Czajkowski (ICCVG, 2018)

Efficient Data Streaming for a Tightly-Coupled Coarse-Grained Reconfigurable Array. - Mahdi Abbaszadeh; Tarek S. Abdelrahman; Reza Azimi; Tomasz S. Czajkowski; Maziar Goudarzi (IPDPS Workshops, 2023)

ACPO: AI-Enabled Compiler-Driven Program Optimization. - Amir H. Ashouri; Muhammad Asif Manzoor; Duc Minh Vu; Raymond Zhang; Ziwen Wang; Angel Zhang; Bryan Chan; Tomasz S. Czajkowski; Yaoqing Gao (CoRR, 2023)

Work-in-Progress:ACPO: An AI-Enabled Compiler Framework. - Amir H. Ashouri; Muhammad Asif Manzoor; Minh Vu; Raymond Zhang; Ziwen Wang; Angel Zhang; Bryan Chan; Tomasz S. Czajkowski; Yaoqing Gao (CASES, 2024)

RoDMap: A Reserve-on-Demand Mapper for Spatially-Configured Coarse-Grained Reconfigurable Arrays. - Kyle Zhao Bin Chen; Tarek S. Abdelrahman; Reza Azimi; Tomasz S. Czajkowski; Maziar Goudarzi (ICPP, 2024)