Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture. - Tomoaki Konishi; Hiroyuki Yotsuyanagi; Masaki Hashizume (3DIC, 2011)

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. - Masaki Hashizume; Tomoaki Konishi; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (Asian Test Symposium, 2013)