Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. - Yoshiki Saito; Tomoaki Shirai; Takuro Nakamura; Takashi Nishimura; Yohei Hasegawa; Satoshi Tsutsumi; Toshihiro Kashima; Mitsutaka Nakata; Seidai Takeda; Kimiyoshi Usami; Hideharu Amano (FPT, 2008)