Dynamic binary code translation for data prefetch optimization. - Tomoaki Ukezono; Kiyofumi Tanaka (ACSAC, 2008)

HDOS: An Infrastructure for Dynamic Optimization. - Tomoaki Ukezono; Kiyofumi Tanaka (PDPTA, 2008)

Reduction of leakage energy in low level caches. - Tomoaki Ukezono; Kiyofumi Tanaka (Green Computing Conference, 2010)

Filtering Insertions into a Small Instruction Cache in Embedded Processors. - Tomoaki Ukezono (CANDAR, 2013)

Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ICCD, 2017)

A low-power high-speed accuracy-controllable approximate multiplier design. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ASP-DAC, 2018)

An Error Corrector for Dynamically Accuracy-Configurable Approximate Adder. - Tomoaki Ukezono (CANDAR Workshops, 2018)

A Low-Power Yet High-Speed Configurable Adder for Approximate Computing. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ISCAS, 2018)

Approximate Adder Generation for Image Processing Using Convolutional Neural Network. - Ryuta Ishida; Toshinori Sato; Tomoaki Ukezono (ISOCC, 2018)

Exploiting Configurability for Correct Sign Calculation in an Approximate Adder. - Toshinori Sato; Tomoaki Ukezono (ISOCC, 2018)

A low-power configurable adder for approximate applications. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ISQED, 2018)

A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing. - Hiroyuki Baba; Tongxin Yang; Masahiro Inoue; Kaori Tajima; Tomoaki Ukezono; Toshinori Sato (ISVLSI, 2018)

Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Correcting Sign Calculation Errors in Configurable Approximations. - Toshinori Sato; Tomoaki Ukezono (APCCAS, 2019)

Tolerating Aging-Induced Timing Violations Via Configurable Approximations. - Toshinori Sato; Tomoaki Ukezono (GCCE, 2019)

Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ACM Great Lakes Symposium on VLSI, 2019)

A Low-Power Approximate Multiply-Add Unit. - Tongxin Yang; Toshinori Sato; Tomoaki Ukezono (ISDCS, 2019)

An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. - Tongxin Yang; Toshinori Sato; Tomoaki Ukezono (ISVLSI, 2019)

On Applications of Configurable Approximation to Irregular Voltage. - Toshinori Sato; Tomoaki Ukezono (NORCAS, 2019)

Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance. - Toshinori Sato; Tomoaki Ukezono (PRDC, 2019)

Trading Accuracy for Power with a Configurable Approximate Adder. - Toshinori Sato; Tongxin Yang; Tomoaki Ukezono (IEICE Trans. Electron., 2019)

Design and Analysis of Approximate Multipliers with a Tree Compressor. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Evaluations of CMA with Error Corrector in Image Processing Circuit. - Tomoaki Ukezono (Int. J. Netw. Comput., 2019)

A Dynamically Configurable Approximate Array Multiplier with Exact Mode. - Toshinori Sato; Tomoaki Ukezono (ICCCS, 2020)

An Accuracy-Configurable Adder for Low-Power Applications. - Tongxin Yang; Toshinori Sato; Tomoaki Ukezono (IEICE Trans. Electron., 2020)

Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations. - Toshinori Sato; Tomoaki Ukezono (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs. - Masaki Sano; Kenta Shirane; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Tongxin Yang; Tomoaki Ukezono (ISOCC, 2021)

An Accuracy-Controllable Approximate Adder for FPGAs. - Masaki Sano; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ATAIT, 2022)

Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge. - Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ACM Great Lakes Symposium on VLSI, 2022)

An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES. - Yui Koyanagi; Tomoaki Ukezono (ISOCC, 2022)

A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design. - Yui Koyanagi; Tomoaki Ukezono (CANDARW, 2023)

Reusing Outputs from S-Boxes for Tamper Resistant Design. - Tomoaki Ukezono; Yui Koyanagi (ICECET, 2023)

Effect of High Frequency Noise Using DCMs in FPGA on Power Analysis Attack. - Tomoaki Ukezono; Yui Koyanagi (ISCIT, 2023)

Negative Impact of Approximated Signed Addition on Power Reduction. - Hiroyuki Hama; Tomoaki Ukezono; Toshinori Sato (ISDCS, 2023)

Leveraging Approximate Computing for IoT Image Transmission. - Hiroyuki Hama; Tomoaki Ukezono; Toshinori Sato (ISOCC, 2023)

Investigation for Impact of Environmental Noise on Power Analysis Attacks. - Ryoma Katsube; Tomoaki Ukezono (ISOCC, 2023)

Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition. - Toshinori Sato; Hiroyuki Hama; Tomoaki Ukezono (ISOCC, 2023)

A Cost-Sensitive and Simple Masking Design for Side-Channels. - Yui Koyanagi; Tomoaki Ukezono (TENCON, 2023)

Flattening Power Waveforms by Hamming Distance Converter for Side-channel Attacks. - Ryoma Katsube; Taiki Nagatomo; Tomoaki Ukezono (APCCAS, 2024)

Random Clock Gating for Side-channel Protection. - Yui Koyanagi; Tomoaki Ukezono (APCCAS, 2024)

An OS Support for Tamper-Resistant Software Execution Using Empty Interruptions. - Soma Kato; Yui Koyanagi; Tomoaki Ukezono (ICISS, 2024)

A Light-weight and Tamper-resistant AES Implementation by FPGAs. - Yui Koyanagi; Tomoaki Ukezono; Toshinori Sato (ISCAS, 2024)

A Light-weight Random Number Generation for Tamper-resistant AES Circuit. - Tomoaki Ukezono; Yui Koyanagi (Int. J. Netw. Comput., 2024)