An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. - Masaki Momodomi; Yasuo Itoh; Riichiro Shirota; Yoshihisa Iwata; Ryozo Nakayama; Ryouhei Kirisawa; Tomoharu Tanaka; Seiichi Aritome; Tetsuo Endoh; Kazunori Ohuchi; Fujjo Masuoka (IEEE J. Solid State Circuits, 1989)

A high-density NAND EEPROM with block-page programming for microcomputer applications. - Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Yasuo Itoh; Ryozo Nakayama; Ryouhei Kirisawa; Seiichi Aritome; Tetsuo Endoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 4 Mb NAND EEPROM with tight programmed Vt distribution. - Masaki Momodomi; Tomoharu Tanaka; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Yasuo Itoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. - Tomoharu Tanaka; Yoshiyuki Tanaka; Hiroshi Nakamura; Koji Sakui; Hideko Oodaira; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka; Hisashi Hara (IEEE J. Solid State Circuits, 1994)

A double-level-Vth select gate array architecture for multilevel NAND flash memories. - Ken Takeuchi; Tomoharu Tanaka; Hiroshi Nakamura (IEEE J. Solid State Circuits, 1996)

A stable programming pulse generator for single power supply flash memories. - Toru Tanzawa; Tomoharu Tanaka (IEEE J. Solid State Circuits, 1997)

A dynamic analysis of the Dickson charge pump circuit. - Toru Tanzawa; Tomoharu Tanaka (IEEE J. Solid State Circuits, 1997)

A compact on-chip ECC for low cost flash memories. - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Riichiro Shirota; Seiichi Aritome; Hiroshi Watanabe; Gertjan Hemink; Kazuhiro Shimizu; Shinji Sato; Yuji Takeuchi; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1997)

A multipage cell architecture for high-speed programming multilevel NAND flash memories. - Ken Takeuchi; Tomoharu Tanaka; Toru Tanzawa (IEEE J. Solid State Circuits, 1998)

A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. - Ken Takeuchi; Shinji Satoh; Tomoharu Tanaka; Ken-ichi Imamiya; Koji Sakui (IEEE J. Solid State Circuits, 1999)

A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. - Ken Takeuchi; Tomoharu Tanaka (IEEE J. Solid State Circuits, 2001)

Circuit techniques for a 1.8-V-only NAND flash memory. - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Hiroshi Nakamura (IEEE J. Solid State Circuits, 2002)

A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. - Raymond Zeng; Navneet Chalagalla; Dan Chu; Daniel Elmhurst; Matt Goldman 001; Chris Haid; Atif Huq; Takaaki Ichikawa; Joel Jorgensen; Owen Jungroth; Nishnat Kajla; Ravinder Kajley; et al. (ISSCC, 2009)

A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories. - Toru Tanzawa; Tomoharu Tanaka; Satoru Tamada; Jiro Kishimoto; Sjigekazu Yamada; Koichi Kawai; Takaaki Ichikawa; P. Chiang; Frank Roohparvar (ESSCIRC, 2010)

Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors. - Toru Tanzawa; T. Murakoshi; T. Kamijo; Tomoharu Tanaka; J. J. McNeil; K. Duesman (A-SSCC, 2016)

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. - Tomoharu Tanaka; Mark Helm; Tommaso Vali; Ramin Ghodsi; Koichi Kawai; Jae-Kwan Park; Shigekazu Yamada; Feng Pan; Yuichi Einaga; Ali Ghalam; Toru Tanzawa; Jason Guo; et al. (ISSCC, 2016)