An ultrahigh-speed full adder using resonant-tunneling logic gates. - Takao Waho; Hiroki Okuyama; Tomohiko Ebata; Ryousuke Kato (APCCAS, 2008)

Enhancement of comparator operation speed by using negative-differential-resistance devices. - Tomohiko Ebata; Uichiro Omae; Kazuya Machida; Keita Hoshi; Takao Waho (ISCAS, 2010)

A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller. - Tetsuo Matsui; Keisaku Sento; Tomohiko Ebata; Atsuhiko Ishibashi (ESSCIRC, 2019)

A 16-bit SAR ADC with Capacitor Dielectric Relaxation Effect Canceler in a 22-nm Microcontroller for Multi-Input Channel Applications. - Tomohiko Ebata; Atsushi Ochi; Iori Sakai; Cheng Yuan; Takanobu Nimiya; Daiki Matsumoto; Qiaoyu Wang; Shinsuke Yoshimura; Tetsuo Matsui (A-SSCC, 2024)