Transition from two-word to multiple-word stage in the course of language acquisition. - Tomohiko Ito (ICSLP, 1994)

Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. - Tomohiko Ito; Takafumi Yamaji; Daisuke Kurose; Tetsuro Itakura (IEICE Electron. Express, 2004)

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. - Tomohiko Ito; Takeshi Ueno; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Electron. Express, 2005)

Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. - Tomohiko Ito; Daisuke Kurose; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. - Daisuke Kurose; Tomohiko Ito; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEEE J. Solid State Circuits, 2006)

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. - Tomohiko Ito; Daisuke Kurose; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Electron., 2008)

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. - Takeshi Ueno; Tomohiko Ito; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers. - Tomohiko Ito; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (ISSCC, 2012)

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Masaomi Iwanaga; Yosuke Ogasawara; Tomohiko Ito; Daisuke Kurose; Naotaka Koide; Toru Hashimoto; Hiroki Sakurai; Takafumi Yamaji; et al. (VLSIC, 2012)

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2012)

Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication". - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2013)

An infinite-resolution grid snapping technique based on fuzzy theory. - Ten Watanabe; Tomohito Yoshikawa; Tomohiko Ito; Yuto Miwa; Takeshi Shibata; Sato Saga (Appl. Soft Comput., 2020)

Over-sketching Operation to Realize Geometrical and Topological Editing across Multiple Objects in Sketch-based CAD Interface. - Tomohiko Ito; Teruyoshi Kaneko; Yoshiki Tanaka; Sato Saga (IUI Companion, 2021)

An interactive sketch-based CAD interface realizing geometrical and topological editing across multiple objects based on fuzzy logic. - Tomohiko Ito; Teruyoshi Kaneko; Yoshiki Tanaka; Sato Saga (Comput. Graph., 2022)