A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. - Yoshifumi Ikenaga; Masahiro Nomura; Shuji Suenaga; Hideo Sonohara; Yoshitaka Horikoshi; Toshiyuki Saito; Yukio Ohdaira; Yoichiro Nishio; Tomohiro Iwashita; Miyuki Satou; Koji Nishida; Koichi Nose; et al. (IEEE J. Solid State Circuits, 2012)

Experimental Implementation of 8.9Kgate Stress Monitor in 28nm MCU Along with Safety Software Library for IoT Device Maintenance. - Kan Takeuchi; Masaki Shimada; Shinya Konishi; Daisuke Oshida; Naoya Ota; Takashi Yasumasu; Koji Shibutani; Tomohiro Iwashita; Tetsuya Kokubun; Fumio Tsuchiya (IRPS, 2019)