Interrupt handling in the loosely synchronized TMR system. - Tomohiro Yoneda; Takashi Suzuoka; Yoshihiro Tohma (Syst. Comput. Jpn., 1985)

A fast timing verification method based on the independence of units. - Tomohiro Yoneda; Kazutoshi Nakade; Yoshihiro Tohma (FTCS, 1989)

Acceleration of timing verification method based on time petri nets. - Tomohiro Yoneda; Yoshihiro Tohma; Yutaka Kondo (Syst. Comput. Jpn., 1991)

Efficient Verification of Parallel Real-Time Systems. - Tomohiro Yoneda; Atsufumi Shibayama; Bernd-Holger Schlingloff; Edmund M. Clarke (CAV, 1993)

Using partial orders for trace theoretic verification of asynchronous circuits. - Tomohiro Yoneda; Takashi Yoshikawa (ASYNC, 1996)

BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. - Tomohiro Yoneda; Hideyuki Hatori; Atsushi Takahara; Shin-ichi Minato (FMCAD, 1996)

Efficient Verification of Parallel Real-Time Systems. - Tomohiro Yoneda; Bernd-Holger Schlingloff (Formal Methods Syst. Des., 1997)

Verification of asynchronous logic circuit design using process algebra. - Tomohiro Yoneda; Atsufumi Shibayama; Takashi Nanya (Syst. Comput. Jpn., 1997)

Verification of Parameterized Asynchronous Circuits: A Case Study. - Tomohiro Yoneda; Yutaka Ohtsuka; Märt Saarepera (ACSD, 1998)

Verification of Bounded Delay Asynchronous Circuits with Timed Traces. - Tomohiro Yoneda; Bin Zhou; Bernd-Holger Schlingloff (AMAST, 1998)

A Self-Timed Implementation of Boolean Functions. - Märt Saarepera; Tomohiro Yoneda (ASYNC, 1999)

Timed Trace Theoretic Verification Using Partial Order Reduction. - Tomohiro Yoneda; Hiroshi Ryu (ASYNC, 1999)

Verification of Abstracted Instruction Cache of TITAC2: A Case Study. - Tomohiro Yoneda (VLSI, 1999)

VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. - Tomohiro Yoneda (CAV, 2000)

Conformance and mirroring for timed asychronous circuits. - Bin Zhou; Tomohiro Yoneda; Bernd-Holger Schlingloff (ASP-DAC, 2001)

Framework of Timed Trace Theoretic Verification Revisited. - Bin Zhou; Tomohiro Yoneda; Chris J. Myers (Asian Test Symposium, 2001)

Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. - Tomoya Kitai; Tomohiro Yoneda (PRDC, 2001)

Verification of asynchronous circuits based on zero-suppressed BDDs. - Koichi Masukura; Minoru Tomisaka; Tomohiro Yoneda (Syst. Comput. Jpn., 2001)

Efficient verification by exploiting symmetry and abstraction. - Hiroshi Toshima; Tomohiro Yoneda (Syst. Comput. Jpn., 2001)

Automatic Derivation of Timing Constraints by Failure Analysis. - Tomohiro Yoneda; Tomoya Kitai; Chris J. Myers (CAV, 2002)

Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. - Tomoya Kitai; Yusuke Oguro; Tomohiro Yoneda; Eric Mercer; Chris J. Myers (PRDC, 2002)

Modular Synthesis of Timed Circuits using Partial Order Reduction. - Eric Mercer; Chris J. Myers; Tomohiro Yoneda (Theory and Practice of Timed Systems @ ETAPS, 2002)

Modular Synthesis of Timed Circuits Using Partial Order Reduction. - Tomohiro Yoneda; Eric Mercer; Chris Myers (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Synthesis of Speed Independent Circuits Based on Decomposition. - Tomohiro Yoneda; Hiroomi Onda; Chris J. Myers (ASYNC, 2004)

Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. - Scott Little; David Walter; Nicholas Seegmiller; Chris J. Myers; Tomohiro Yoneda (ATVA, 2004)

High Level Synthesis of Timed Asynchronous Circuits. - Tomohiro Yoneda; Atsushi Matsumoto; Manabu Kato; Chris J. Myers (ASYNC, 2005)

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. - Tomoya Kitai; Tomohiro Yoneda; Chris J. Myers (IEICE Trans. Inf. Syst., 2005)

Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. - Denduang Pradubsuwun; Tomohiro Yoneda; Chris J. Myers (IEICE Trans. Inf. Syst., 2005)

ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. - Hiroshi Saito; Nattha Jindapetch; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (CIT, 2006)

Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. - Tomohiro Yoneda; Chris J. Myers (ATVA, 2006)

Verification of analog/mixed-signal circuits using labeled hybrid petri nets. - Scott Little; Nicholas Seegmiller; David Walter; Chris J. Myers; Tomohiro Yoneda (ICCAD, 2006)

Verification of timed circuits with failure-directed abstractions. - Hao Zheng 001; Chris J. Myers; David Walter; Scott Little; Tomohiro Yoneda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Symbolic Model Checking of Analog/Mixed-Signal Circuits. - David Walter; Scott Little; Nicholas Seegmiller; Chris J. Myers; Tomohiro Yoneda (ASP-DAC, 2007)

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. - Hiroshi Saito; Naohiro Hamada; Nattha Jindapetch; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. - Curtis A. Nelson; Chris J. Myers; Tomohiro Yoneda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Synthesis of Timed Circuits Based on Decomposition. - Tomohiro Yoneda; Chris J. Myers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). - Naohiro Hamada; Yuki Shiga; Hiroshi Saito; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (ACSD, 2008)

Hazard Checking of Timed Asynchronous Circuits Revisited. - Frédéric Béal; Tomohiro Yoneda; Chris J. Myers (Fundam. Informaticae, 2008)

A Conservative Framework for Safety-Failure Checking. - Frédéric Béal; Tomohiro Yoneda; Chris J. Myers (IEICE Trans. Inf. Syst., 2008)

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. - David Walter; Scott Little; Chris J. Myers; Nicholas Seegmiller; Tomohiro Yoneda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

N-way ring and square arbiters. - Masashi Imai; Tomohiro Yoneda; Takashi Nanya (ICCD, 2009)

Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. - Hao Zheng 001; Haiqiong Yao; Tomohiro Yoneda (ISVLSI, 2009)

A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. - Naohiro Hamada; Yuki Shiga; Takao Konishi; Hiroshi Saito; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. - Hiroshi Saito; Naohiro Hamada; Tomohiro Yoneda; Takashi Nanya (ISCAS, 2010)

Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol. - Chammika Mannakkara; Tomohiro Yoneda (IEICE Trans. Inf. Syst., 2010)

Preface. - Kedar S. Namjoshi; Tomohiro Yoneda (Int. J. Found. Comput. Sci., 2010)

Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement. - Hao Zheng 001; Haiqiong Yao; Tomohiro Yoneda (IEEE Trans. Computers, 2010)

Improving Dependability and Performance of Fully Asynchronous On-chip Networks. - Masashi Imai; Tomohiro Yoneda (ASYNC, 2011)

Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. - Masashi Imai; Tomohiro Yoneda (DFT, 2011)

A Dynamic Link-Width Optimization for Network-on-Chip. - Daihan Wang; Michihiro Koibuchi; Tomohiro Yoneda; Hiroki Matsutani; Hideharu Amano (RTCSA (2), 2011)

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. - Scott Little; David Walter; Chris J. Myers; Robert A. Thacker; Satish Batchu; Tomohiro Yoneda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Dependable routing in multi-chip NoC platforms for automotive applications. - Tomohiro Yoneda; Masashi Imai (DFT, 2012)

An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. - Hiroshi Saito; Tomohiro Yoneda; Yuichi Nakamura 002 (MCSoC, 2012)

Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. - Masashi Imai; Tomohiro Yoneda (PRDC, 2012)

Multi-chip NoCs for Automotive Applications. - Tomohiro Yoneda; Masashi Imai; Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (PRDC, 2012)

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. - Masashi Imai; Tomohiro Yoneda (IEICE Trans. Inf. Syst., 2013)

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). - Tomohiro Yoneda; José Flich Cardo; Jiang Xu 001; Michihiro Koibuchi (NII Shonan Meet. Rep., 2013)

Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. - Masashi Imai; Tomohiro Yoneda (APCCAS, 2014)

An NoC-based evaluation platform for safety-critical automotive applications. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Takahiro Hanyu; Kenji Kise; Yuichi Nakamura 002 (APCCAS, 2014)

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. - Zhen Zhang 006; Wendelin Serwe; Jian Wu; Tomohiro Yoneda; Hao Zheng 001; Chris J. Myers (FMICS, 2014)

Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. - Masashi Imai; Tomohiro Yoneda (ISCAS, 2014)

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. - Naoya Onizawa; Akira Mochizuki; Hirokatsu Shirahama; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2014)

Dependable real-time task execution scheme for a many-core platform. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Kenji Kise (DFTS, 2015)

A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. - Tomohiro Yoneda; Masashi Imai (ICCD, 2015)

Novel Implementation Method of Multiple-Way Asynchronous Arbiters. - Masashi Imai; Tomohiro Yoneda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A task allocation method for the DTTR scheme based on task scheduling of fault patterns. - Hiroshi Saito; Masashi Imai; Tomohiro Yoneda (ISCAS, 2016)

A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. - Hiroshi Saito; Masashi Imai; Tomohiro Yoneda (MCSoC, 2016)

Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance. - Sarat Yoowattana; Tomohiro Yoneda (MCSoC, 2016)

The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. - Masashi Imai; Thiem Van Chu; Kenji Kise; Tomohiro Yoneda (NOCS, 2016)

An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. - Zhen Zhang 006; Wendelin Serwe; Jian Wu; Tomohiro Yoneda; Hao Zheng 001; Chris J. Myers (Sci. Comput. Program., 2016)

Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. - Hai-Phong Phan; Xuan-Tu Tran; Tomohiro Yoneda (ICICDT, 2017)

Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. - Hiroshi Saito; Masashi Imai; Tomohiro Yoneda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. - Masashi Imai; Shinichiro Akasaka; Tomohiro Yoneda (ASYNC, 2018)

MTJ-based asynchronous circuits for Re-initialization free computing against power failures. - Naoya Onizawa; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (Microelectron. J., 2018)

Hardware Trojan Insertion and Detection in Asynchronous Circuits. - Koutaro Inaba; Tomohiro Yoneda; Toshiki Kanamoto; Atsushi Kurokawa; Masashi Imai (ASYNC, 2019)

Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). - Tomohiro Yoneda; Peter A. Beerel; Alex Yakovlev; Masashi Imai (NII Shonan Meet. Rep., 2019)

Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. - Tomohiro Yoneda; Masashi Imai (ASYNC, 2020)

A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. - Yuji Yamada; Nesrine Berjab; Tomohiro Yoneda; Kenji Kise (MCSoC, 2023)

An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. - Daisuke Suzuki; Akira Tamakoshi; Tomohiro Yoneda; Masanori Natsui; Yasuhiro Takako; Takahiro Hanyu (ISMVL, 2025)

Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. - Tomohiro Yoneda; Yasuhiro Takako; Akira Tamakoshi; Masanori Natsui; Daisuke Suzuki; Takahiro Hanyu (ISMVL, 2025)