A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. - Hisakatsu Yamaguchi; Hirotaka Tamura; Yoshiyasu Doi; Yasumoto Tomita; Takayuki Hamada; Masaya Kibune; Shuhei Ohmoto; Keita Tateishi; Oleksiy Tyshchenko; Ali Sheikholeslami; Tomokazu Higuchi; Junji Ogawa; et al. (ISSCC, 2010)

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Tomoyuki Arai; Yutaka Ide; Kazuhiro Terashima; Hirohito Higashi; Tomokazu Higuchi; et al. (A-SSCC, 2015)

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hisakatsu Yamaguchi; et al. (VLSI Circuits, 2016)

ClPy: A NumPy-Compatible Library Accelerated with OpenCL. - Tomokazu Higuchi; Naoki Yoshifuji; Tomoya Sakai 003; Yoriyuki Kitta; Ryousei Takano; Tsutomu Ikegami; Kenjiro Taura (IPDPS Workshops, 2019)